Error detection schemes for a unified cache in a data processing system

A method comprising:

• providing processing circuitry for executing a plurality of data processing instructions;
• coupling a unified cache memory to the processing circuitry for storing data and instructions processed by the processing circuitry, the unified cache memory comprising a plurality of sets, each set comprising a plurality of ways, each way comprising one or more information fields;
• coupling a cache memory control circuitry to the unified cache memory;
• and
• providing control circuitry for allocating each way of the unified cache memory for one of:
• (1) a first type of information;
• (2) a second type of information;
• or (3) both the first type of information and the second type of information, the control circuitry further individually controlling a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon a result of the allocating.

A data processing system comprising:

• a processing unit for executing a plurality of data processing instructions;
• a unified cache memory coupled to the processing unit for storing data and instructions processed by the processing circuitry, the unified cache memory comprising a plurality of ways, each way comprising a plurality of lines, each line comprising an information field;
• first control circuitry coupled to the unified cache memory and comprising an allocation control register for allocating each way of the plurality of ways for either a first type of information or a second type of information, or for both the first type of information and the second type of information;
• and
• second control circuitry coupled to the first control circuitry for further individually selecting a mode of error detection for each way of the unified cache memory based upon the allocating performed by the first control circuitry.