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US 2010/0064143 A1Published application
System lsi
AssigneeKabushiki Kaisha Toshiba
InventorNaoaki Ohkubo
Life of this patent
Estimating the term…
Abstract
A system LSI comprising: a processor which processes confidential data; a first on-chip bus which is connected to the processor; a working memory which saves the confidential data processed by the processor; and a memory interface circuit which is connected between the first on-chip bus and the working memory, and through which data is transferred between the working memory and the first on-chip bus under control of the processor.
Claims17
A system LSI comprising:
- a processor which processes confidential data;
- a first on-chip bus which is connected to the processor;
- a working memory which saves the confidential data processed by the processor;
- and
- a memory interface circuit which is connected between the first on-chip bus and the working memory, and through which data is transferred between the working memory and the first on-chip bus under control of the processor.
2 more elements
A system LSI comprising:
- a main processor;
- a main memory;
- a main bus which is connected to the main processor and to the main memory;
- a sub-processor which performs an encryption-decryption process on data;
- a working memory which saves confidential data created in the encryption-decryption process;
- a sub bus which is connected to the sub-processor;
- an interface circuit which is connected to the sub bus and to the working memory, and which prohibits or permits data transfer between the sub bus and the working memory under control of the sub-processor;
- and
- a bus bridge which is connected to the main bus and to the sub bus, and which controls data transfer between the main bus and the sub bus.
6 more elements
A system LSI comprising:
- a main processor;
- a main bus which is connected to the main processor;
- a first debug interface circuit which is connected to the main bus, and to which a first debugger is connected during debugging of the main processor;
- a sub-processor which performs an encryption-decryption process on data;
- a sub bus which is connected to the sub-processor;
- a second debug interface circuit which is connected to the sub bus, and to which a second debugger is connected during debugging of the sub-processor;
- and
- a bus bridge which is connected to the main bus and to the sub bus, and through which data is transferred between the main bus and the sub bus under control of a debug mode signal outputted from the first debug interface circuit.
5 more elements
Dependencies are inferred from the claim text.