Replay Reduction for Power Saving

A processor comprising:

• a scheduler configured to issue a first instruction operation to be executed;
• and
• a memory management unit coupled to receive the first instruction operation, and wherein the memory management unit is configured to replay the first instruction operation responsive to detecting a miss in a translation buffer within the memory management unit for the first instruction operation;
• wherein the scheduler, in response to an initial detection of the replay from the memory management unit for the first instruction operation, is configured to reissue the first instruction operation after at least a predetermined delay and without receiving an acknowledgement indication, and wherein the predetermined delay is sufficient for the memory management unit to search a next level translation buffer structure and load a translation into the translation buffer in response to a hit in the next level translation buffer structure.

A method comprising:

• issuing a first instruction operation to be executed;
• detecting a first replay case of a plurality of replay cases by a first replay source of a plurality of replay sources during execution of the first instruction operation, wherein each of the plurality of replay sources is configured to detect one or more of the plurality of replay cases, and wherein the first replay case is one of a subset of the plurality of replay cases for which an acknowledgement indication is provided;
• inhibiting reissuance of the first instruction operation subsequent to the replay of the first instruction operation for the first replay case until the acknowledgement indication corresponding to the first replay case is provided;
• and
• issuing a second instruction operation during a time that the first instruction operation is inhibited from reissuing, wherein the second instruction operation is subsequent to the first instruction operation in program order.

A method comprising:

• issuing a first instruction operation to be executed;
• replaying the first instruction operation responsive to detecting a miss in a translation buffer of a memory management unit for the first instruction operation;
• in response to the replaying, reissuing the first instruction operation after at least a predetermined delay and without receiving an acknowledgement indication;
• and
• during the predetermined delay, the memory management unit searching a next level translation buffer structure and loading a translation into the translation buffer in response to a hit in the next level translation buffer.