Method and Apparatus for Reducing Latency Associated with Executing Multiple Instruction Groups
AssigneeVNS Portfolio LLC
InventorCharles H. Moore
Life of this patent
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Abstract
A method and apparatus for reducing latency in computer processors. The method incorporates a special instruction set that provides an indication of whether a particular instruction is capable of being executed nearly simultaneously with a preceding instruction in the same group. In such a situation, multiple instructions may be executed at a rate faster than expected. A simple apparatus for accomplishing this method is illustrated.
Claims22
A system for reducing latency in a computer processor executing a stream of instruction by reducing latency associated with waiting for fetching of instructions until a prior instruction is executed comprising:
- an instruction set including a plurality of memory instructions and a plurality of arithmetic logic unit instructions wherein the arithmetic logic unit instructions are distinguishable from the memory instructions;
- and a comparator in said computer processor for distinguishing arithmetic logic unit instructions from memory instructions;
- and wherein said comparator fetches arithmetic logic unit instructions substantially coincident with the execution of a prior arithmetic logic unit instruction to reduce latency associated with waiting for fetching of instructions until a prior instruction is executed.
A method for reducing latency in computer processing of a stream of incoming information groups having a plurality of instructions comprising the steps of loading an incoming information group and determining if the loaded instruction group contains any arithmetic logic instructions, and fetching the next incoming information group substantially coincident with the execution of the arithmetic logic instruction, and determining if the next loaded instruction group contains and continuing the process until all instructions are loaded and executed.
A computer processor for loading and executing a stream of incoming information groups comprising a loader for loading incoming information groups into a register;
- and a comparator for determining if an incoming instruction is an arithmetic logic instruction and immediately fetching the next instruction if the previous instruction was an arithmetic logic instruction.
Dependencies are inferred from the claim text.