Information processing device including memory management device managing access from processor to memory and memory management method

An information processing device including a memory management device, comprising:

• an accepting section which accepts a write destination logical address and write target data from a processor, the write destination logical address indicating a write position to write the write target data into a composite memory which includes a first memory and a nonvolatile second memory;
• an address determining section which determines a write destination physical address corresponding to the write destination logical address so that the number of times of access to the second memory is smaller than the number of times of access to the first memory;
• an address management section which stores, in a storage section, address conversion data associating the write destination logical address with the write destination physical address;
• and
• a writing section which writes the write target data into a position in the composite memory indicated by the write destination physical address.