Microprocessor cache line evict array
AssigneeVIA Technologies, Inc.
InventorsColin Eddy, Rodney E. Hooker
Life of this patent
Estimating the term…
Abstract
An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy includes an eviction engine and an array of storage elements. The eviction engine is configured to move the cache line from the lower-level memory to the higher-level memory. The array of storage elements are coupled to the eviction engine. Each storage element is configured to store an indication for a corresponding cache line stored in the lower-level memory. The indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.
Claims25
An apparatus for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy, the apparatus comprising:
- an eviction engine, configured to move the cache line from the lower-level memory to the higher-level memory;
- an array of storage elements, coupled to the eviction engine, each configured to store an indication for a corresponding cache line stored in the lower-level memory, wherein the indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.
A method for ensuring data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy, the method comprising:
- moving the cache line from the lower-level memory to the higher-level memory, wherein the moving is performed by an eviction engine;
- storing into an array of storage elements an indication for a corresponding cache line stored in the lower-level memory, wherein the indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.
A computer program product for use with a computing device, the computer program product comprising:
- a computer usable storage medium, having computer readable program code embodied in said medium, for specifying a microprocessor configured to ensure data coherency within a cache memory hierarchy of a microprocessor during an eviction of a cache line from a lower-level memory to a higher-level memory in the hierarchy, the computer readable program code comprising:
- first program code for specifying an eviction engine, configured to move the cache line from the lower-level memory to the higher-level memory;
- and
- second program code for specifying an array of storage elements, configured to store an indication for a corresponding cache line stored in the lower-level memory, wherein the indication indicates whether or not the eviction engine is currently moving the cache line from the lower-level memory to the higher-level memory.
Dependencies are inferred from the claim text.