Data processor and data processing system

A data processor comprising:

• an instruction fetch section for fetching an instruction;
• an instruction decoder for decoding the instruction fetched by the instruction fetch section;
• and
• an executor for executing the instruction, based on a result of decoding by the instruction decoder,
• wherein the instruction fetch section comprises an instruction buffer and a branch prediction unit,
• wherein the instruction buffer comprises a memory unit for storing each instruction fetched from outside and a buffer controller for controlling the memory unit, and
• wherein when an execution history of a fetched condition branch instruction suggests condition establishment, and in the case that a branch direction of the fetched condition branch instruction corresponds to a direction opposite to the order of an instruction execution and a difference of instruction addresses from the branch source to the branch target based on the condition branch instruction is a range held in a storage capacity of the memory unit, the buffer controller retains, in the memory unit, an instruction sequence from a branch source to a branch target based on the condition branch instruction, supplies each instruction of the instruction sequence from the memory unit to the instruction decoder while an instruction execution of the instruction sequence retained therein is repeated, and releases retention of the instruction sequence when the instruction execution is exited from the instruction sequence.