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US 2010/0064101 A1Published application
Memory controller and data processing system
AssigneeHitachi, Ltd.
InventorsSEIJI MIURA, Kazushige AYUKAWA
Life of this patent
Estimating the term…
Abstract
A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performed at a high speed and low power consumption.
Claims8
1-27. (canceled)
A semiconductor device comprising:
- a memory controller coupled to a volatile memory, which has a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, the volatile memory being controlled to automatically pre-charge the plurality of bit lines after a read access in a first mode and not to automatically pre-charge the plurality of bit lines after a read access in a second mode, and including a counter which counts a number of successive accesses to different word lines,
- wherein the memory controller changes from the second mode to the first mode after different word lines are accessed a predetermined number of times successively, a number of the predetermined time being set in the counter.
Dependencies are inferred from the claim text.