Systems, methods, and apparatuses for in-band data mask bit transmission
AssigneeIntel Corporation
InventorKuljit S. Bains
Life of this patent
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Abstract
Embodiments of the invention are generally directed to systems, methods, and apparatuses for in-band data mask bit transmission. In some embodiments, one or more data mask bits are integrated into a partial write frame and are transferred to a memory device via the data bus. Since the data mask bits are transferred via the data bus, the system does not need (costly) data mask pin(s). In some embodiments, a mechanism is provided to enable a memory device (e.g., a DRAM) to check for valid data mask bits before completing the partial write to the DRAM array.
Claims24
An integrated circuit comprising:
- logic to issue a partial write command to a volatile memory device;
- and
- logic to generate a partial write frame responsive to the partial write command, wherein the partial write frame includes m unit intervals to transfer partial write data and n unit intervals to transfer data mask bits and further wherein at least some of the data mask bits are repeated in more than one of the n unit intervals.
An integrated circuit comprising:
- a memory core;
- input/output logic coupled with the memory core, the input/output logic capable of receiving a partial write frame including m unit intervals of partial write data and n unit intervals of data mask bits, wherein a first unit interval of the n unit intervals includes a first set of data mask bits and a second unit interval of the n unit intervals includes a second set of data mask bits;
- and
- enable logic coupled with the input/output logic, the enable logic to enable a write to the memory core based, at least in part, on whether the first set of data mask bits matches the second set of data mask bits.
A method comprising:
- issuing a partial write command to a volatile memory device;
- generating a partial write frame responsive to the partial write command, wherein the partial write frame includes m unit intervals to transfer partial write data and n unit intervals to transfer data mask bits and further wherein at least some of the data mask bits are repeated in more than one of the n unit intervals;
- and
- transferring the partial write frame to the volatile memory device.
A system comprising:
- a host including
- logic to issue a partial write command to a dynamic random access memory device, and
- logic to generate a partial write frame responsive to the partial write command, wherein the partial write frame includes m unit intervals to transfer partial write data and n unit intervals to transfer data mask bits and further wherein at least some of the data mask bits are repeated in more than one of the n unit intervals;
- and
- the dynamic random access memory device to receive the partial write data frame.
The system of claim, wherein the dynamic random access memory device includes
- a memory core;
- input/output logic coupled with the memory core, the input/output logic capable of receiving the partial write frame;
- and
- enable logic coupled with the input/output logic, the enable logic to enable a write to the memory core based, at least in part, on whether the n data mask bit sets match.
Dependencies are inferred from the claim text.