Flash memory storage system
AssigneeHitachi, Ltd.
InventorsTakashige IWAMURA, Kazuhisa Fujimoto, Yoshiaki Eguchi, Shunji Kawamura
Life of this patent
Estimating the term…
Abstract
A flash memory storage system has a plurality of flash memory devices comprising a plurality of flash memories, and a controller having an I/O processing control unit for accessing a flash memory device specified by a designated access destination in an I/O request received from an external device from among the plurality of flash memory devices. A parity group can be configured of flash memory devices having identical internal configuration.
Claims20
-19. (canceled)
A storage controller coupled to a plurality of flash memory devices (FMDs), each FMD including a plurality of flash memories, and receiving and processing an I/O request from an external device, said storage controller comprising:
- a processor for accessing an FMD specified by a designated access destination in said received I/O request, from among said plurality of FMDs,
- wherein two or more parity groups are configured of two or more FMDs from among said plurality of FMDs,
- wherein FMDs having different internal configurations are included in said plurality of FMDs, and
- wherein each parity group is configured of FMDs, each FMD having an identical internal configuration.
A storage controller coupled to a plurality of flash memory devices (FMDs), each FMD including a plurality of flash memories, and receiving and processing an I/O request from an external device, said storage controller comprising:
- a processor for accessing an FMD specified by a designated access destination in said received I/O request, from among said plurality of FMDs,
- wherein two or more parity groups are configured of two or more FMDs from among said plurality of FMDs,
- wherein FMDs having different internal configurations are included in said plurality of FMDs,
- wherein each parity group is configured of FMDs, each FMD having an identical internal configuration, and
- wherein when the processor detects that an FMD from among said plurality of FMDs has been blocked, the processor specifies a parity group to which said blocked FMD belongs, searches for an alternative FMD corresponding to said parity group, recovers data stored in said blocked FMD, and writes said recovered data into the alternative FMD.
A storage controller coupled to a plurality of flash memory devices (FMDs), each FMD including a plurality of flash memories, and receiving and processing an I/O request from an external device, said storage controller comprising:
- a processor for accessing an FMD specified by a designated access destination in said received I/O request, from among said plurality of FMDs,
- wherein said processor checks whether or not the internal configurations of a plurality of FMDs designated from said external device as configuration elements of a parity group are identical and outputs an alarm to said external device when the internal configurations are not identical.
A storage controller coupled to a plurality of flash memory devices (FMDs), each FMD including a plurality of flash memories, and receiving and processing an I/O request from an external device, said storage controller comprising:
- a processor for accessing an FMD specified by a designated access destination in said received I/O request, from among said plurality of FMDs;
- and
- a cache memory,
- wherein when said I/O request is a read request, said processor reads data from said plurality of FMDs according to said read request, temporarily accumulates the data that have been read out in said cache memory, then sends the data accumulated in said cache memory to said external device, and checks the correctness of data accumulated in said cache memory when said data that has been read is accumulated in said cache memory.
A storage controller coupled to a plurality of flash memory devices (FMDs), each FMD including a plurality of flash memories, and receiving and processing an I/O request from an external device, said storage controller comprising:
- a processor for accessing an FMD specified by a designated access destination in said received I/O request, from among said plurality of FMDs,
- wherein a plurality of address spaces are hierarchized, and block sizes in each layer are different, and
- wherein a flash memory from among said plurality of flash memories, an FMD from among said plurality of FMDs, a parity group configured of two or more FMDs from among said plurality of FMDs, and a logical storage unit to be provided to said external device are present as a layer.
Dependencies are inferred from the claim text.