Interface for writing to memories having different write times

An interface for memories having different write times, comprising in combination:

• means for monitoring whether a processor accesses a first memory device;
• means for capturing data and address information from a memory access;
• means for determining whether to store the data associated with the memory access in a second memory device, wherein the second memory device is a hardened latch that includes a logic circuit and a storage element, wherein an amount of energy that can be stored in the storage element is greater than an amount of energy that can be removed by an event upset;
• means for determining an address in the second memory device to which the data is to be stored upon determining that the data is to be stored in the second memory device;
• and
• enable logic for writing the data to the first memory device and the second memory device during the same processor bus cycle, wherein the enable logic adjusts the write timing to compensate for the difference in write times between the first and second memories, wherein the time required to write the data to the second memory device is greater than the time required to write the data to the first memory device.

A method for providing an interface between memory devices having different write speeds, comprising in combination:

• monitoring communication between a processor and a first memory device;
• when the processor writes data to an address in the first memory device, latching the data and the address;
• determining whether the data is to be stored in a second memory device, wherein the second memory device is a hardened latch that includes a logic circuit and a storage element, wherein an amount of energy that can be stored in the storage element is greater than an amount of energy that can be removed by an event upset;
• if the data is to be stored in the second memory device, determining an address for storing the data in the second memory device;
• and
• writing the data in the address of the first memory device and the second memory device during the same processor bus cycle, wherein writing the data in the address of second memory device comprises adjusting the write timing to compensate for the difference in write times between the first and second memories, wherein the time required to write the data to the second memory device is greater than the time required to write the data to the first memory device.