Method and apparatus for handling of clock information in serival link ports
AssigneeInternational Business Machines Corporation
InventorsPeter Buchmann, Martin Leo Schmatz
Life of this patent
Estimating the term…
Abstract
A receiver for a serial link port that is enhanced by a clock-data-recovery loop connected to the forwarded clock signal lane. The receiver includes a phase interpolation means controlled by a phase position logic which gets its update signal from local phase update signals of the clock-data-recovery loop via a digital low pass filter. The receiver also provides a global phase update source selection logic to control which clock-data-recovery loop is distributing phase update information, and which clock-data-recovery loop is receiving phase update information based on the clock analysis block.
Claims20
Receiver apparatus for a serial link, comprising:
- a first clock-data-recovery loop having a digitally controlled phase adjuster comprising recovery means to recover data and generation means to generate information about a phase difference between an input phase signal and a clock phase signal;
- a clock generator having a digitally controlled second phase adjuster to adjust a phase of said clock generator;
- a distributor to distribute phase difference information in digital form between said first clock-data-recovery loop and said digitally controlled second phase adjuster of said clock generator;
- and
- a synchronizer to transfer recovered data to a clock domain with a clock derived from said digitally controlled second phase adjuster of said clock generator.
A method for handling of clock information in a receiver of a serial link, the method comprising the steps of:
- recovering data via a first clock-data-recovery loop having a digitally controlled phase adjuster;
- generating information about a phase difference between an input phase and a clock phase;
- adjusting a phase of a clock generator having a digitally controlled second phase adjuster;
- distributing said phase difference information in digital form between said first clock-data-recovery loop and said digitally controlled phase adjuster of said clock generator;
- and
- transferring said recovered data to a clock domain with a clock derived from said digitally controlled phase adjuster of said clock generator.
A serial data transmission link system having at least one receiver comprising:
- a first clock-data-recovery loop having a digitally controlled phase adjuster comprising recovery means to recover data and generation means to generate information about a phase difference between an input phase signal and a clock phase signal;
- a clock generator having a digitally controlled second phase adjuster to adjust a phase of said clock generator;
- a distributor to distribute phase difference information in digital form between said first clock-data-recovery loop and said digitally controlled second phase adjuster of said clock generator;
- and
- a synchronizer to transfer recovered data to a clock domain with a clock derived from said digitally controlled second phase adjuster of said clock generator.
A serial data transmission link system having a plurality of data lanes plus a forwarded clock signal lane each having a receiver comprising:
- a first clock-data-recovery loop having a digitally controlled phase adjuster comprising recovery means to recover data and generation means to generate information about a phase difference between an input phase signal and a clock phase signal;
- a clock generator having a digitally controlled second phase adjuster to adjust a phase of said clock generator;
- a distributor to distribute phase difference information in digital form between said first clock-data-recovery loop and said digitally controlled second phase adjuster of said clock generator;
- and
- a synchronizer to transfer recovered data to a clock domain with a clock derived from said digitally controlled second phase adjuster of said clock generator.
Dependencies are inferred from the claim text.