Reduced Frequency Data Processing Using a Matched Filter Set Front End

A method for data detection using a reduced rate clock, the method comprising:

• receiving a series of symbols at a rate corresponding to an input clock;
• filtering the series of symbols in parallel through a first matched filter, a second matched filter, a third matched filter and a fourth matched filter;
• and wherein the first matched filter is tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, the second matched filter is tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence, the third matched filter is tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, and the fourth matched filter is tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence;
• and
• performing a data detection on a series of symbol proxies including the first symbol proxy, the second symbol proxy, the third symbol proxy and the fourth symbol proxy at a rate corresponding to the input clock divided by a factor.

A communication system including a receiver with a reduced rate data detector, the system comprising:

• a receiver, wherein the receiver includes:
• an analog to digital converter, wherein the analog to digital converter is operable to receive an analog signal and to generate a series of digital samples representing the analog signal at a rate corresponding to an input clock;
• a matched filter bank, wherein the matched filter bank receives a series of symbols derived from the series of digital samples and filters the received series of symbols through a first matched filter tuned to detect a first bit sequence in the series of symbols and to assert a first symbol proxy upon detection of the first bit sequence, a second matched filter tuned to detect a second bit sequence in the series of symbols and to assert a second symbol proxy upon detection of the second bit sequence, a third matched filter tuned to detect a third bit sequence in the series of symbols and to assert a third symbol proxy upon detection of the third bit sequence, and a fourth matched filter tuned to detect a fourth bit sequence in the series of symbols and to assert a fourth symbol proxy upon detection of the fourth bit sequence;
• and
• a detector, wherein the detector processes a series of symbol proxies including the first symbol proxy, the second symbol proxy, the third symbol proxy and the fourth symbol proxy at a rate corresponding to the input clock divided by a factor.