Data processing apparatus and data processing system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorPhil Jae Jeon
Life of this patent
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Abstract
In a data processing apparatus and a data processing system including the same, the data processing apparatus includes a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal; and a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data.
Claims20
A data processing apparatus comprising:
- a clock signal generation unit configured to receive a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized valid data, to generate a synchronous clock signal that is synchronized with the serialized valid data based on the data signal, and to generate at least one sample clock signal based on the synchronous clock signal;
- and
- a data processor configured to deserialize the serialized valid data based on the at least one sample clock signal, to decode deserialized data based on the DC balance codes, and to output decoded data.
A data processing apparatus comprising:
- an encoder configured to receive parallel data, at least one synchronous signal, and a clock signal and to DC-balance the parallel data;
- and
- a serializer configured to serialize DC-balanced data output from the encoder and to generate a data signal comprising a preamble signal, DC balance codes comprising DC balance information, and information about serialized data,
- wherein the serializer embeds the clock signal between the DC balance codes.
A data processing system comprising:
- a master configured to receive parallel data, at least one synchronous signal, and a clock signal and to generate a data signal comprising a preamble signal, information about DC balance codes for DC balance, an embedded clock signal between the DC balance codes, and information about serialized data;
- and
- a slave configured to receive the data signal, to generate a synchronous clock signal that is synchronized with the serialized data comprised in the data signal, and to deserialize the serialized data based on the synchronous clock signal,
- wherein the master DC-balances the parallel data and outputs DC-balanced data as the serialized data.
Dependencies are inferred from the claim text.