Digital pulse width modulator
AssigneePowervation Limited
InventorsEamon O'malley, Karl Rinne
Life of this patent
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Abstract
A DPWM (1) has a delay lock loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each of eight delay cells (35). A multiplexer (5) selects one of the delay cell outputs at any one time. This allows the DPWM (1) to have eight times the resolution which would otherwise be achieved with the same input clock. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.
Claims21
A switched mode power converter controller (SMPCC) for providing a PWM control signal to a power switch in a switching cycle,
- the SMPCC controller having a hybrid Digital Pulse Width Modulator (DPWM), the hybrid DPWM effecting the PWM control signal at a switching point at a resolution of N bits across the switching cycle,
- the hybrid DPWM comprising:
- a) a counter circuit responsive to a clock signal and determining the switching point at a resolution of N-M bits, the counter circuit providing an enable output signal at the determined switching point,
- b) a locked loop for delaying the clock signal to provide M clock phases from the clock signal,
- c) a multiplexer for selecting one of the M clock phases to provide a multiplexor output in response to a received select signal,
- d) an output control element having the multiplexor output as an input, wherein the control element is enabled by the enable output signal from the controller, and wherein the controller generates the multiplexor select signal so as to provide the PWM control signal at an effective resolution of N bits.
A switched mode power converter controller (SMPCC) for providing a plurality of control signals for operating individual power switches within a switching cycle of a switching converter,
- the SMPC controller having a hybrid Digital Pulse Width Modulator (DPWM), the hybrid DPWM generating each of the control signals at switching points across the switching cycle at a resolution of N bits,
- the hybrid DPWM comprising:
- a) a counter circuit responsive to a clock signal,
- b) a plurality of controllers comprising a plurality of comparators, each of the comparators being associated with an individual control signal and determining the switching point of the control signal at a resolution less than N and providing individual enabled signals at said determined switching points,
- c) a locked loop for delaying the clock signal to provide a plurality of clock phases from the clock signal,
- d) a plurality of output control elements, each of the individual control elements being enabled by an enable signal received from an associated comparators,
- e) a plurality of multiplexers, each of the multiplexors for selecting one of the clock phases and providing an input to one of the output control elements in response to a select signal received from an associated controller, wherein the controller determines the value of said select signal to increase the effective resolution of the DPWM to N bits.
A switched mode power converter controller (SMPCC) for providing a PWM control signal to a power switch in a switching cycle,
- the SMPCC controller having a hybrid Digital Pulse Width Modulator (DPWM), the hybrid DPWM effecting the PWM control signal at a switching point at a resolution of N bits across the switching cycle, the hybrid DPWM comprising:
- a) a counter circuit responsive to a clock signal and providing a counter value,
- b) a programmable module responsive to the counter value and determining the occurrence of the switching point from the counter value using the M most significant bits of the switching point, the programmable module providing an enable output signal at the determined occurrence, the programmable module providing a phase select signal with the N-M least significant bits of the switching point,
- c) a locked loop for delaying the clock signal to provide a plurality of clock phases from the clock signal,
- d) a multiplexer responsive to the phase select signal for selecting one of the clock phases to provide a multiplexor output in response to a received select signal,
- e) an output control element having the multiplexor output as an input, wherein the control element is enabled by the enable output signal from the programmable module.
Dependencies are inferred from the claim text.