Decision feedback equalizer having clock recovery circuit and method for recovering clock

A decision feedback equalizer for a high speed serial communication system, comprising:

• a combiner configured to combine received data with feedback data and output the combined data as equalization data;
• a decision circuit configured to decide recovery data by receiving the equalization data;
• a feedback loop configured to supply the recovery data to the combiner as feedback data;
• and
• a clock recovery circuit configured to detect whether edges of feedback data components exist within a window with a size previously defined at each edge of received data components of the equation data, recover a clock with respect to the edges of the received data components and the other edges of the feedback data components except the detected edges and supply the recovered clock for decision operation of the decision circuit.

A decision feedback equalizer for a high speed serial communication system, comprising:

• a combiner configured to combine received data with feedback data and output the combined data as equalization data;
• a decision circuit configured to decide recovery data by receiving the equalization data;
• a feedback loop configured to supply the recovery data to the combiner as feedback data;
• and
• a clock recovery circuit configured to remove a delay data component from the equalization data through the feedback loop, recover a clock with respect to the other equalization data except the delay data component and supply the recovered clock for decision operation of the decision circuit.