# US 2010/0060767 A1 · Analog-signal processing circuit for improving accuracy of arithmetic mean of signals > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2010/0060767 A1 - Document ID: US20100060767A1 - Status: Published application - Kind: A1 - Application number: 12/555,229 - Filed: 2009-09-08 - Published: 2010-03-11 - Earliest claimed: 2008-09-10 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Ryuta OKAMOTO - Web page: https://patentgrep.com/patent/US20100060767A1 ## CPC - H04N 25/77: Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract In a first signal conversion circuit, a first electrode of a first capacitor is connected to a first signal line, and a second electrode thereof is connected to a first node. In a second capacitor, a third electrode thereof is connected to a second signal line, and a fourth electrode thereof is connected to a second node. In a first inverting amplifier including a first negative feedback switch, a first input electrode is connected to the first node, and a first output electrode is connected to a third node. In a second inverting amplifier including a second negative feedback switch, a second input electrode is connected to the second node. A first averaging switch is connected between a first node and second node. A second averaging switch is connected between third node and fourth node. ## Claims ### Claim 1 An analog signal processing circuit comprising: a first signal line; a second signal line; and a first signal conversion circuit connected to the first and second signal lines, wherein the first signal conversion circuit comprises a first capacitor a first electrode of which is connected to the first signal line, and a second electrode of which is connected to a first node; a second capacitor a third electrode of which is connected to the second signal line, and a fourth electrode of which is connected to a second node; a first inverting amplifier a first input electrode of which is connected to the first node, a first output electrode of which is connected to a third node, and which includes a first negative feedback switch; a second inverting amplifier a second input electrode of which is connected to the second node, a second output electrode of which is connected to a fourth node, and which includes a second negative feedback switch; a first averaging switch configured to connect between the first node and second node; and a second averaging switch configured to connect between the third node and fourth node. ### Claim 2 (depends on 1) The circuit according to claim 1, wherein the first signal conversion circuit further comprises a first T/D converter connected to the third node; a second T/D converter connected to the fourth node; a ramp signal line; a first switch connected between the first signal line and first electrode, the first switch being controlled by a first control signal; a second switch connected between the second signal line and third electrode, the second switch being controlled by the first control signal; a third switch connected between the ramp signal line and a fifth node, the third switch being controlled by a second control signal; a fourth switch connected between the ramp signal line and a sixth node, the fourth switch being controlled by the second control signal; a third capacitor a fifth electrode of which is connected to the fifth node, and a sixth electrode of which is connected to the first electrode; and a fourth capacitor a seventh electrode of which is connected to the sixth node, and an eighth electrode of which is connected to the third electrode. ### Claim 3 (depends on 1) The circuit according to claim 1, wherein the first signal conversion circuit further comprises a third capacitor a fifth electrode of which is connected to the first node, and a sixth electrode of which is connected to the third node; and a fourth capacitor a seventh electrode of which is connected to the second node, and an eighth electrode of which is connected to the fourth node. ### Claim 4 (depends on 1) The circuit according to claim 1, wherein the first signal conversion circuit further comprises a ramp generator circuit configured to supply a reference potential of the first and second inverting amplifiers; a first T/D converter connected to the third node; and a second T/D converter connected to the fourth node. ### Claim 5 (depends on 1) The circuit according to claim 1, further comprising a drive circuit configured to control third, fourth, and fifth control signals, wherein the third control signal controls the first averaging switch, fourth control signal controls the second averaging switch, and fifth control signal controls the first and second negative feedback switches. ### Claim 6 (depends on 1) The circuit according to claim 1, further comprising: a first odd-numbered column signal line; a first even-numbered column signal line; a second odd-numbered column signal line; a second even-numbered column signal line; a first changeover switch configured to connect one of the first odd-numbered column signal line and first even-numbered column signal line to the first signal line; and a second changeover switch configured to connect one of the second odd-numbered column signal line and second even-numbered column signal line to the second signal line. ### Claim 7 (depends on 1) The circuit according to claim 1, further comprising: a third changeover switch configured to connect a column signal line different from the column signal line connected by the first changeover switch to a third signal line; a fourth changeover switch for connecting a column signal line different from the column signal line connected by the second changeover switch to a fourth signal line; and a second signal conversion circuit connected to the third and fourth signal lines, configured identical with the first signal conversion circuit. ### Claim 8 (depends on 7) The circuit according to claim 7, wherein the first signal conversion circuit further comprises a first T/D converter connected to the third node; a second T/D converter connected to the fourth node; a ramp signal line; a first switch connected between the first signal line and first electrode, the first switch being controlled by a first control signal; a second switch connected between the second signal line and third electrode, the second switch being controlled by the first control signal; a third switch connected between the ramp signal line and a fifth node, the third switch being controlled by a second control signal; a fourth switch connected between the ramp signal line and a sixth node, the fourth switch being controlled by a second control signal; a third capacitor a fifth electrode of which is connected to the fifth node, and a sixth electrode of which is connected to the first electrode; and a fourth capacitor a seventh electrode of which is connected to the sixth node, and an eighth electrode of which is connected to the third electrode. ### Claim 9 (depends on 7) The circuit according to claim 7, wherein the first signal conversion circuit further comprises a third capacitor a fifth electrode of which is connected to the first node, and a sixth electrode of which is connected to the third node; and a fourth capacitor a seventh electrode of which is connected to the second node, and an eighth electrode of which is connected to the fourth node. ### Claim 10 (depends on 7) The circuit according to claim 7, wherein the first signal conversion circuit further comprises a ramp generator circuit configured to supply a reference potential of the first and second inverting amplifiers; a first T/D converter connected to the third node; and a second T/D converter connected to the fourth node. ### Claim 11 A solid-state image pickup device comprising: first and second photoelectric conversion sections for converting light into an electric signal; a first signal line configured to receive an electric signal from the first photoelectric conversion section; a second signal line configured to receive an electric signal from the second photoelectric conversion section; and a signal conversion circuit connected to the first and second signal lines, wherein the signal conversion circuit comprises a first capacitor a first electrode of which is connected to the first signal line, and a second electrode of which is connected to a first node; a second capacitor a third electrode of which is connected to the second signal line, and a fourth electrode of which is connected to a second node; a first inverting amplifier a first input electrode of which is connected to the first node, a first output electrode of which is connected to a third node, and which includes a first negative feedback switch; a second inverting amplifier a second input electrode of which is connected to the second node, a second output electrode of which is connected to a fourth node, and which includes a second negative feedback switch; a first averaging switch configured to connect between the first node and second node; and a second averaging switch configured to connect between the third node and fourth node. ### Claim 12 (depends on 11) The device according to claim 11, wherein the signal conversion circuit further comprises a first T/D converter connected to the third node; a second T/D converter connected to the fourth node; a ramp signal line; a first switch connected between the first signal line and first electrode, the first switch being controlled by a first control signal; a second switch connected between the second signal line and third electrode, the second switch being controlled by the first control signal; a third switch connected between the ramp signal line and a fifth node, the third switch being controlled by a second control signal; a fourth switch connected between the ramp signal line and a sixth node, the fourth switch being controlled by the second control signal; a third capacitor a fifth electrode of which is connected to the fifth node, and a sixth electrode of which is connected to the first electrode; and a fourth capacitor a seventh electrode of which is connected to the sixth node, and an eighth electrode of which is connected to the third electrode. ### Claim 13 (depends on 11) The device according to claim 11, wherein the signal conversion circuit further comprises a third capacitor a fifth electrode of which is connected to the first node, and a sixth electrode of which is connected to the third node; and a fourth capacitor a seventh electrode of which is connected to the second node, and an eighth electrode of which is connected to the fourth node. ### Claim 14 (depends on 11) The device according to claim 11, wherein the signal conversion circuit further comprises a ramp generator circuit configured to supply a reference potential of the first and second inverting amplifiers; a first T/D converter connected to the third node; and a second T/D converter connected to the fourth node. ### Claim 15 (depends on 11) The device according to claim 11, further comprising a drive circuit connected to control third, fourth, and fifth control signals, wherein the third control signal controls the first averaging switch, fourth control signal controls the second averaging switch, and fifth control signal controls the first and second negative feedback switches. ### Claim 16 A solid-state image pickup device comprising: first, second, third, and fourth photoelectric conversion sections for converting light into an electric signal; a first signal line configured to convert an electric signal from the first photoelectric conversion section; a second signal line configured to receive an electric signal from the second photoelectric conversion section; a third signal line configured to receive an electric signal from the third photoelectric conversion section; a fourth signal line for receiving an electric signal from the fourth photoelectric conversion section; a first switch arranged at one ends of the first signal line and second signal line, the first switch connecting one of the first and second signal lines to a fifth signal line; a second switch arranged at one ends of the third signal line and fourth signal line, the second switch connecting one of the third and fourth signal lines to a sixth signal line; a third switch arranged at the other ends of the first signal line and second signal line, the third switch connecting the other one of the first and second signal lines to a seventh signal line; a fourth switch arranged at the other ends of the third signal line and fourth signal line, the fourth switch connecting the other one of the third and fourth signal lines to an eighth signal line; a first signal conversion circuit connected to a first node connected to the fifth signal line, and a second node connected to the sixth signal line; and a second signal conversion circuit connected to a first node connected to the seventh signal line, and a second node connected to the eighth signal line, wherein each of the first and second signal conversion circuits comprises a first capacitor a first electrode of which is connected to the first node, and a second electrode of which is connected to a third node; a second capacitor a third electrode of which is connected to the second node, and a fourth electrode of which is connected to a fourth node; a first inverting amplifier a first input electrode of which is connected to the third node, a first output electrode of which is connected to a fifth node, and which includes a first negative feedback switch; a second inverting amplifier a second input electrode of which is connected to the fourth node, a second output electrode of which is connected to a sixth node, and which includes a second negative feedback switch; a first averaging switch configured to connect between the third node and fourth node; and a second averaging switch configured to connect between the fifth node and sixth node. ### Claim 17 (depends on 16) The device according to claim 16, wherein each of the first and second signal conversion circuits further comprises a first T/D converter connected to the fifth node; a second T/D converter connected to the sixth node; a ramp signal line; a first switch controlled by a first control signal, connected between one of the first node and the first electrode; a second switch controlled by the first control signal, connected between the second node and the third electrode; a third switch controlled by a second control signal, connected between the ramp signal line and a seventh node; a fourth switch controlled by the second control signal, connected between the ramp signal line and an eighth node; a third capacitor a fifth electrode of which is connected to the seventh node, and a sixth electrode of which is connected to the first electrode; and a fourth capacitor a seventh electrode of which is connected to the eighth node, and an eighth electrode of which is connected to the third electrode. ### Claim 18 (depends on 16) The device according to claim 16, wherein each of the first and second signal conversion circuits further comprises a third capacitor a fifth electrode of which is connected to the third node, and a sixth electrode of which is connected to the fifth node; and a fourth capacitor a seventh electrode of which is connected to the fourth node, and an eighth electrode of which is connected to the sixth node. ### Claim 19 (depends on 16) The device according to claim 16, wherein each of the first and second signal conversion circuits further comprises a ramp generator circuit configured to supply a reference potential of the first and second inverting amplifiers; a first T/D converter connected to the fifth node; and a second T/D converter connected to the sixth node. ### Claim 20 (depends on 16) The device according to claim 16, further comprising: a first drive circuit configured to control third, fourth, and fifth control signals; and second drive circuit configured to control sixth, seventh, and eighth control signals, wherein the third control signal controls the first averaging switch in the first signal conversion circuit, the fourth control signal controls the second averaging switch in the first signal conversion circuit, the fifth control signal controls the first and second negative feedback switches in the first signal conversion circuit, the sixth control signal controls the first averaging switch in the second signal conversion circuit, the seventh control signal controls the second averaging switch in the second signal conversion circuit, and the eighth control signal controls the first and second negative feedback switches in the second signal conversion circuit.