Successive approximation type a/d converter, method of controlling successive approximation type a/d converter, solid-state imaging device, and imaging apparatus

A solid-state imaging device comprising a successive approximation type A/D converter converting an analog signal output from a pixel including a photoelectric conversion element into a digital signal, wherein the successive approximation type A/D converter includes:

• a reference signal generating section generating a reference signal;
• a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into an N-bit digital signal;
• and
• a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N-n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.

An imaging apparatus comprising:

• a solid-state imaging device including a successive approximation type A/D converter converting an analog signal output from a pixel including a photoelectric conversion element into a digital signal;
• and
• an optical system forming an image of incident light on an imaging surface of the solid-state imaging device, wherein the successive approximation type A/D converter includes:
• a reference signal generating section generating a reference signal,
• a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into an N-bit digital signal, and
• a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N-n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.