Minimizing adverse effects of skew between two analog-to-digital converters
AssigneeMobius Semiconductor, Inc.
InventorsAvanindra Madisetti, Thomas D. Kwon, Aaron W. Buchwald
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Abstract
Skew between a first clock signal received by a first analog-to-digital converter (ADC) and a second clock signal received by a second ADC is adjusted to minimize error. Each ADC has an ADC element that produces a respective first or second digital output signal in response to an analog input signal and a respective first or second clock signal. A correction signal is produced in response to the first and second digital output signals. The skew between the first and second clock signals is then adjusted in response to the correction signal.
Claims15
An analog-to-digital converter (ADC) system, comprising:
- a first ADC comprising a first ADC element, the first ADC element producing a first digital output signal in response to a first analog signal representing a signal to be converted and a first clock signal representing a master clock signal;
- a second ADC comprising a second ADC element, the second ADC element producing a second digital output signal in response to a second analog signal representing the signal to be converted and a second clock signal representing the master clock signal;
- a correction estimator, the correction estimator producing a correction signal in response to the first digital output signal and the second digital output signal;
- and
- a timing adjuster, the timing adjuster adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.
An analog-to-digital converter (ADC) system, comprising:
- a first ADC comprising a first ADC element, the first ADC element producing a first digital output signal in response to a first analog signal representing a signal to be converted and a first clock signal representing a master clock signal;
- a second ADC comprising a second ADC element, the second ADC element producing a second digital output signal in response to a second analog signal representing the signal to be converted and a second clock signal representing the master clock signal;
- a slope detector for producing a slope factor representing a slope of the input analog signal, the slope detector comprising a delay system and a comparator system, the delay system producing a plurality of samples of the analog input signal delayed by different amounts from each other, the comparator system comparing the plurality of samples of the analog input signal with the first analog signal;
- a correction estimator, the correction estimator comprising gain logic for producing a gain signal, offset logic for producing an offset signal, and correction logic for producing a correction signal, the correction estimator further comprising a subtractor, an adder and a multiplier, the subtractor producing an error signal in response to a skew estimate and an output of one of the first ADC and second ADC, the adder adding the offset signal to an output of the multiplier to produce the skew estimate, and the multiplier multiplying an output of an other one of the first ADC and second ADC by the gain signal, wherein the offset logic produces the offset signal in response to a previous offset signal value and previous error signal value and produces the gain signal in response to a previous gain signal value, a previous error signal value and a previous sampled value;
- and
- a timing adjuster, the timing adjuster adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.
A method of operation of a system comprising a first analog-to-digital converter (ADC) having a first ADC element and a second ADC having a second ADC element, the method comprising:
- the first ADC element producing a first digital output signal in response to a first analog signal representing a signal to be converted and a first clock signal representing a master clock signal;
- the second ADC element producing a second digital output signal in response to a second analog signal representing the signal to be converted and a second clock signal representing the master clock signal;
- producing a correction signal in response to the first digital output signal and the second digital output signal;
- and
- adjusting a skew between the first clock signal and the second clock signal in response to the correction signal.
Dependencies are inferred from the claim text.