Bias generator providing for low power, self-biased delay element and delay line
AssigneeMosaid Technologies Incorporated
InventorPeter A. VLASENKO
Life of this patent
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Abstract
An improved bias generator incorporates a reference voltage and/or a reference current into the generation of bias voltages. In some cases, the output of a biased delay element has a constant voltage swing. A delay line of such constant output voltage swing delay elements may be shown to provide reduced power consumption compared to some known self-biased delay lines. Furthermore, in other cases, providing the reference current to a novel bias generator allows a delay line of delay elements biased by such a novel bias generator to show reduced sensitivity to operating conditions, reduced sensitivity to variation in process parameters and improved signal quality, thereby providing more robust operation.
Claims14
A bias generator for biasing delay elements in a delay line employing one or more delay elements, said bias generator comprising:
- a bias generator variable resistance load element, said bias generator variable resistance load element connected between a power supply voltage and a given node;
- a voltage-controlled current source for generating a reference current, said voltage-controlled current source formed of a reference current generator supplying a reference current to a differential pair of field effect transistors (FETs), where division of said reference current between said pair of FETs is based on a reference voltage on a first branch and a control voltage on a second branch;
- and
- a first current mirror formed of a first side and a second side, said first side connected to said voltage-controlled current source so that current in said first side and current in said second side are established based on said division of said reference current.
At a bias generator, a method of controlling delay in delay elements in a delay line employing one or more delay elements, said method comprising:
- generating a reference current;
- supplying said reference current to a differential pair of field effect transistors (FETs), said pair of FETs including a first FET and a second FET, such that a first portion of said reference current flows through said first FET and a second portion of said reference current flows through said second FET;
- applying a reference voltage to a gate of said first FET;
- applying a control voltage to a gate of said second FET;
- and
- receiving, at a first side of a first current mirror formed of said first side and a second side, said second portion of said reference current.
Dependencies are inferred from the claim text.