Power supply insensitive voltage level translator
AssigneeFairchild Semiconductor Corporation
InventorsHrvoje Jasa, Steven M. Macaluso, Julie Stultz, Roy L. Yarbrough
Life of this patent
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Abstract
A circuit is described that when the power supply to circuits that control a pass transistor is at zero volts, the pass transistor configured as a voltage level translator remains off regardless of the voltages and changes in voltages at the ports connected to the pass transistor. Cross coupled transistors provide a mechanism where the higher of the port voltages is available to power circuitry that maintains the control input of the pass transistor in the off condition. The voltages at the ports may rise and fall relative to each other, but the control input of the pass transistor will keep the pass transistor off.
Claims8
A voltage level translator comprising:
- a pass transistor having a control input and two ports or contacts each connected to circuits that transfer signals to each other via the pass transistor when the pass transistor is on, and wherein the signals may be of different voltages;
- two cross coupled transistors each having a control input connected to one of the ports of the pass transistor and with outputs from each of the cross coupled transistors connected together to form a first output, wherein the cross coupling is configured to transfer the higher of the port voltages to the first output;
- a control circuit having a control output, the control circuit powered by a power voltage, the control circuit connected to the first output;
- an inverter with an input and an output, wherein the first output is transferred via the control circuit to the inverter input;
- and wherein the inverter output is connected to the control input of the pass transistor;
- and, when the power voltage to the control circuit is at or near zero volts, the inverter output is maintained low holding the pass transistor is off regardless of the value or transitions of the port voltages.
A process for keeping a voltage level translator, having two ports and a control input, in the off condition when the voltage powering a control circuit, that turns the voltage level translator on or off, falls to or near zero, the process comprising the steps of:
- positioning the voltage level translator between two circuits that develop different voltages at each port;
- selecting the higher of the voltages at the ports;
- presenting the selected voltage to the control circuit;
- and
- maintaining the off condition to the voltage translator, when the control circuit has voltage translator off, and then power to the control circuit falls to or near zero.
Dependencies are inferred from the claim text.