US 2010/0060335 A1 · Seamless Coarse and Fine Delay Structure for High Performance DLL

Abstract

A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a single coarse delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. The coarse delay line may have a hierarchical or a non-hierarchical structure. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The coarse shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Claims19

Dependent claims

A method of producing a clock signal, comprising:

generating a plurality of first and second intermediate clocks having a fixed phase difference therebetween from a reference clock using a delay line;
inputting each of said first and second intermediate clocks to a first level of switches;
inputting an output from said first level of switches to a second level of switches, wherein said second level of switches has fewer switches than said first level of switch;
and
inputting an output from said second level of switches to a phase mixer, said phase mixer generating an output clock from said first and said second intermediate clocks, wherein said output clock has a phase between the phases of said first and said second intermediate clocks.

2 more elements

Dependencies are inferred from the claim text.

Seamless Coarse and Fine Delay Structure for High Performance DLL

Life of this patent

Seamless Coarse and Fine Delay Structure for High Performance DLL

Life of this patent

Abstract

Claims19