Dll circuit and control method therefor

A DLL circuit comprising:

• a delay line receiving an external signal, the delay line variably setting a delay time with a prescribed delay time unit, based on a selection control signal which controls a delay of the external signal, the delay line producing a first set of first and second delay signals having different delay time values in association with a first transition of the external signal, the delay line producing a second set of first and second delay signals having different delay time values in association with a second transition of the external signal;
• a first interpolator provided in association with the first set of the first and second delay signals associated with the first transition of the external signal, the first interpolator receiving the first set of the first and second delay signals to output a third delay signal, a delay of the third delay signal being set with a higher resolution than the prescribed delay time unit;
• a second interpolator provided in association with the second set of the first and second delay signals associated with the second transition of the external signal, the second interpolator receiving the second set of the first and second delay signals to output a fourth delay signal, a delay of the fourth delay signal being set with a higher resolution than the prescribed delay time unit;
• a synthesis circuit receiving the third and fourth delay signals output respectively from the first and second interpolators to produce a synthesized output signal, based on the third and fourth delay signals received;
• a duty change detection circuit including a duty change circuit and a duty detection circuit,
• the duty change circuit receiving the synthesized output signal from the synthesis circuit to produce a signal obtained by changing a duty of the output signal of the synthesis circuit in accordance with a duty control signal supplied thereto, the duty being a ratio of HIGH and LOW level periods in one cycle of the output signal of the synthesis circuit,
• the duty detection circuit detecting the duty which is variably controlled by the duty change circuit to output a duty detection result signal including a value indicating whether the duty detected is larger or smaller than a prescribed duty value;
• a selection circuit receiving the duty detection result signal from the duty change detection circuit and a phase comparison result signal from a phase detector that compares the phase of the synthesized output signal from the synthesis circuit and the phase of the external signal to each other, the selection circuit selecting one of the signals received;
• and
• a delay control circuit variably controlling the delay of the delay line and/or the delay of the interpolator corresponding to at least one of the first and second transitions of the external signal, based on an output of the selection circuit.

A method for controlling a DLL (delay locked loop), the method comprising:

• receiving an output signal having a duty value of the DLL;
• generating a signal having a duty value varied, the duty value being a ratio of a HIGH level period and a LOW level period with respect to one period of the DLL output signal;
• and
• comparing the signal with the duty value varied and a reference duty value;
• and
• controlling a delay of a delay control circuit that controls a delay of the DLL in accordance with the result of the comparison.

A DLL (delay locked loop) circuit comprising:

• a first variable delay circuit variably delaying a first transition of an external signal to output a resulting output signal;
• a second variable delay circuit variably delaying a second transition of the external signal to output a resulting output signal;
• a synthesis circuit receiving the output signal of the first variable delay circuit and the output signal of the second variable delay circuit to synthesize the received signals;
• a duty change detection circuit including a duty detection circuit and a duty change circuit, wherein the duty detection circuit includes a capacitor discharged or charged based on an output signal of the synthesis circuit to detect a duty of the output signal of the synthesis circuit using the capacitor, and the duty change circuit changes the duty of the output signal of the synthesis circuit by changing a capacitance value of the capacitor included in the duty detection circuit, the duty being a ratio of a high level period and a low level period relative to one period of the output signal of the synthesis circuit;
• and
• a delay control circuit changing at least one of a delay of the first variable delay circuit and a delay of the second variable delay circuit in accordance with the result of duty detection of the duty change detection circuit.