Digital charge pump pll architecture
AssigneeIcera Canada ULC
InventorsTajinder Manku, Christopher Snyder
Life of this patent
Estimating the term…
Abstract
A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.
Claims24
A digital phase lock loop circuit comprising:
- a voltage controlled oscillator for providing an output clock signal having a first frequency in response to control signals;
- a divider for converting the output clock signal into an internal clock signal having a second frequency;
- a digital charge pump circuit for generating a phase offset word corresponding to a difference in phase between the internal clock signal and a reference clock signal;
- and,
- a digital processing circuit for receiving the phase offset word and for generating the control signals in response to the phase offset word.
A digital charge pump circuit comprising:
- a quantizing circuit for generating a phase offset word in response to a phase difference between active edges of a first signal and a second signal;
- and,
- a phase frequency detector for providing the first signal from a first output terminal in response to a reference clock and the second signal from a second output terminal in response to an internal clock, the first signal having an active edge corresponding to an active edge of the reference clock, and the second signal having an active edge corresponding to an active edge of the internal clock.
Dependencies are inferred from the claim text.