Semiconductor integrated circuit

A semiconductor integrated circuit, comprising:

• a Phase Locked Loop (PLL) circuit configured to generate a PLL clock signal in response to a frequency of a reference clock signal;
• a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal;
• and
• a transmission line configured to transmit the PLL clock signal from the PLL circuit to the voltage controlled oscillator, the transmission line comprising a length that is larger than a sum of a pathway of the reference clock signal from the clock input buffer to the PLL circuit and a transmission length of the output clock signal from the voltage controlled oscillator to the plurality of data input/output buffers.

A semiconductor integrated circuit, comprising:

• a clock input buffer configured to buffer an external clock signal and to generate a reference clock signal;
• a clock generating circuit configured to generate an internal clock signal in response to a frequency of the reference clock signal;
• a voltage controlled oscillator configured to oscillate and output a plurality of output clock signals having multiple phases in response to the internal clock signal;
• and
• a plurality of data input/output buffers configured to receive the plurality of output clock signals to perform buffering operations on input/output data.