US 2010/0060331 A1 · POWER-ON-RESET CIRCUITRY

Abstract

Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.

Claims20

Dependent claims

Power-on-reset circuitry that monitors multiple power supply voltages and that produces a corresponding power-on-reset signal, comprising:

a plurality of comparator-based trip point detectors each of which includes a comparator, wherein the trip point detectors each compare one of the power supply voltages to a respective trip point voltage;
and
power-on-reset controller circuitry that receives an output signal from each of the trip point detectors and that produces the power-on-reset signal in response, wherein the power-on-reset controller circuitry comprises a delay circuit and wherein the power-on-reset controller circuitry is responsive to which order the power supply signals power up.

Power-on-reset circuitry that monitors multiple power supply voltages and that produces a corresponding power-on-reset signal, comprising:

a plurality of comparator-based trip point detectors each of which includes a comparator, wherein the trip point detectors each compare one of the power supply voltages to a respective trip point voltage;
power-on-reset controller circuitry that receives an output signal from each of the trip point detectors and that produces the power-on-reset signal in response;
and
a path that provides a reference voltage to each of the trip point detectors, wherein the trip point detectors generate the respective trip point voltages from the reference voltage, and wherein the trip point detectors comprise an input-output voltage trip point detector that monitors an input-output power supply voltage, a core logic voltage trip point detector that monitors a core logic power supply voltage and a voltage regulator power supply trip point detector that monitors a voltage regulator power supply voltage.

1 more element

Dependencies are inferred from the claim text.

Power-on-reset circuitry

Life of this patent

Power-on-reset circuitry

Life of this patent

Abstract

Claims20