Testing Circuit Split Between Tiers of Through Silicon Stacking Chips
AssigneeQUALCOMM Incorporated
InventorThomas R. Toms
Life of this patent
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Abstract
A method of testing a die having a non-testable circuit, where the non-testable circuit is logically incomplete and forms part of a logically complete multiple tier circuit. The method includes reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit to create a logically complete secondary path for the tier-to-tier point such that the non-testable circuit can be tested. Testable dies and methods of preparing such dies are also provided.
Claims26
A method of testing a die having a non-testable circuit, said non-testable circuit forming a part of a logically complete multiple tier circuit, the method comprising reconfiguring a tier-to-tier input point or tier-to-tier output point associated with a primary path of the non-testable circuit by creating a logically complete secondary path for the tier-to-tier input or output point such that the non-testable circuit can be tested.
A method of preparing a testable die, the method comprising:
- identifying a tier-to-tier input point or a tier-to-tier output point associated with a primary path of a non-testable circuit that forms part of a logically complete multiple tier circuit;
- and
- creating a logically complete secondary path from the identified tier-to-tier input or output point such that the non-testable circuit can be tested;
- wherein the non-testable circuit and the secondary path are located on a single die.
A testable die comprising:
- a non-testable circuit that forms part of a logically complete multiple tier circuit;
- a tier-to-tier input point or a tier-to-tier output point associated with a primary path of the non-testable circuit, the primary path for connecting to another part of the multiple tier circuit on another tier;
- a logically complete secondary path from the tier-to-tier input or output point of the non-testable circuit, for testing the non-testable circuit;
- and
- means to switch from the primary path to the secondary path upon assertion of a test signal.
Dependencies are inferred from the claim text.