Timing generator and semiconductor test apparatus
AssigneeAdvantest Corporation
InventorMasakatsu Suda
Life of this patent
Estimating the term…
Abstract
A variable delay circuit has a simple configuration for being incorporated in a timing generator to control a delay time in real time and assure a timing margin. The variable delay circuit of the timing generator includes a delay circuit having a plurality of cascaded clock buffers; a plurality of cascaded data buffers; and data holding circuits for outputting data to the data buffers in accordance with the clock from the delay circuit. The delay amount added to the data by the data buffers is made identical to the delay amount added to the clock by the clock buffers.
Claims7
A timing generator which is equipped with a variable delay circuit to provide a predetermined delay amount to data and then output the data,
- the variable delay circuit comprising:
- a delay circuit having a plurality of cascaded clock buffers;
- a plurality of AND circuits, each of the AND circuits being provided to correspond to each stage of the delay circuit divided by a predetermined delay time, a clock being input to the AND circuit from the corresponding stage through one input terminal;
- and
- a data buffer, the data buffer being connected to the other input terminals in the plurality of AND circuits, data being input to the data buffer, the data buffer providing a given delay amount to the input data and then sending the data to the AND circuits,
- wherein the delay amount provided to the data by the data buffer is the same as the delay amount provided to the clock by the clock buffer of the stage corresponding to the AND circuit to which this data buffer is connected.
Dependencies are inferred from the claim text.