Semiconductor transistor device with improved isolation arrangement, and related fabrication methods

A method of forming isolation regions in a semiconductor device structure, the method comprising:

• forming an isolation trench in a layer of semiconductor material having an active region adjacent to the isolation trench;
• forming a nitride etch stop layer in the isolation trench;
• covering the nitride etch stop layer with an upper insulating material;
• and
• fabricating a transistor device structure using the active region in the layer of semiconductor material, wherein fabricating the transistor device removes at least some of the upper insulating material in the isolation trench, and leaves at least some of the nitride etch stop layer intact.

An isolation arrangement for a semiconductor device structure, the isolation arrangement comprising:

• a lower layer of insulating material;
• a layer of nitride material overlying the lower layer of insulating material;
• an upper region of insulating material overlying the layer of nitride material;
• and
• a gate structure formed on the upper region of insulating material.