US 2010/0059831 A1 · Spacer-less Low-K Dielectric Processes

Abstract

A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator.

Claims20

Dependent claims

A semiconductor device comprising:

a gate dielectric over a substrate;
a gate over the gate dielectric, wherein the gate comprises exposed gate sidewalls;
and
a first etch stop layer over the substrate.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

12/613,541Filed 6 Nov 2009

Priority

5 Jun 2006

Published

11 Mar 2010

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
H10D 84/0184
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their gate sidewall spacers
H10D 84/0186
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their interconnections or electrodes, e.g. source or drain electrodes

Spacer-less Low-K Dielectric Processes

Life of this patent

Spacer-less Low-K Dielectric Processes

Life of this patent

Abstract

Claims20