Semiconductor device
AssigneesNational University Corporation Tohoku University, Foundation for Advancement of International Scienc E
InventorsTadahiro Ohmi, Akinobu Teramoto, Rihito Kuroda
Life of this patent
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Abstract
In a semiconductor device, the degree of flatness of 0.3 nm or less in terms of a peak-to-valley (P-V) value is realized by rinsing a silicon surface with hydrogen-added ultrapure water in a light-screened state and in a nitrogen atmosphere and a contact resistance of 10−11 Ωcm2 or less is realized by setting a work function difference of 0.2 eV or less between an electrode and the silicon. Thus, the semiconductor device can operate on a frequency of 10 GHz or higher.
Claims48
A semiconductor device wherein a flatness degree of a surface of a channel region in terms of a peak-to-valley value over a length of 2 nm in a direction from a source to a drain is 0.3 nm or less.
A semiconductor device comprising a channel region, a source region and a drain region at both ends of said channel region, and an electrode electrically connected to at least one of said source region and said drain region, characterized in that a resistance from said electrode to said channel region is 4Ω·μm or less.
A semiconductor device comprising at least a pair of an n-channel transistor and a p-channel transistor, wherein
- at least contact portions of first electrodes respectively contacting source and drain regions of said n-channel transistor are formed of a first metal silicide and at least contact portions of second electrodes respectively contacting source and drain regions of said p-channel transistor are formed of a second metal silicide different from said first metal silicide.
A semiconductor device comprising a circuit having at least a pair of transistors of different conductivity types, comprising
- an n-channel transistor having a first semiconductor layer and a first gate insulating layer covering at least a part of a surface of said first semiconductor layer, and a p-channel transistor having a second semiconductor layer and a second gate insulating layer covering at least a part of a surface of said second semiconductor layer,
- wherein a surface of a first region, adapted to form a channel, of said first semiconductor layer has at least one of a (100) plane or a plane within ±10° from the (100) plane and a (110) plane or a plane within ±10° from the (110) plane,
- a surface of a second region, adapted to form a channel, of said second semiconductor layer has at least one of a (110) plane or a plane within ±10° from the (110) plane and a (100) plane or a plane within ±10° from the (100) plane, and
- the surface of each of said first region and said second region has a flatness degree such that a peak-to-valley over a length of 2 nm in a direction from a source to a drain of the corresponding region is 0.3 nm or less.
A semiconductor device comprising a circuit having at least a pair of transistors of different conductivity types, comprising
- an n-channel transistor having a first semiconductor layer and a first gate insulating layer covering at least a part of a surface of said first semiconductor layer, and a p-channel transistor having a second semiconductor layer and a second gate insulating layer covering at least a part of a surface of said second semiconductor layer,
- wherein a surface of a first region, adapted to form a channel, of said first semiconductor layer has at least one of a (100) plane or a plane within ±10° from the (100) plane and a (110) plane or a plane within ±10° from the (110) plane,
- a surface of a second region, adapted to form a channel, of said second semiconductor layer has at least one of a (110) plane or a plane within ±10° from the (110) plane and a (100) plane or a plane within ±10° from the (100) plane,
- a source region and a drain region and further a source electrode and a drain electrode are provided at both ends of each of said first region and said second region, and
- a resistance from each of said first and second regions to each of said source electrode and said drain electrode provided at both ends of the corresponding region is set to 4Ω·μm or less.
Dependencies are inferred from the claim text.