Process for manufacturing a memory device including a vertical bipolar junction transistor and a cmos transistor with spacers

A memory device comprising:

• a semiconductor body having a surface;
• field insulation regions of dielectric material in said body, said field insulation regions delimiting an array portion and a first circuitry portion;
• a bipolar transistor in said array portion, including a first conduction region extending at a distance from said surface, a control region on said first conduction region, a second conduction region surrounded by said control region, and a control contact region surrounded by said control region and spaced apart from said second conduction region;
• a first MOS transistor in said circuitry portion, including first gate structure on said surface, first lightly doped regions in said body, laterally to said first gate structure, first lateral spacers on sides of said first gate structure, third conduction regions in said body, laterally to said lateral spacers, said first lateral spacers comprising lower spacer portions on the sides of said first gate structure and upper spacer portions on and laterally to said lower spacer portions, said lower spacer portions and upper spacer portions forming multilayer spacers;
• and
• a silicide protection mask extending on said array portion and having openings on said second conduction region and control contact region.

A process, comprising:

• manufacturing a memory device having a vertical bipolar transistor and a first MOS transistor in a semiconductor body having a surface, the manufacturing including:
• forming in the body an array portion and a first circuitry portion insulated from each other;
• forming a buried first conduction region of the bipolar transistor, the first conduction region being buried at a distance form the surface of the body;
• forming, on the first conduction region and in the array region, a control region of the bipolar transistor;
• forming, on the surface of the body, a first gate structure of the first MOS transistor;
• forming a dielectric multilayer including first and second dielectric layers extending on said first gate structure and on said control region;
• forming upper spacer portions on sides of said first gate structure by selectively removing said second dielectric layer in said circuitry portion and completely removing said second dielectric layer from said control region;
• after forming the upper spacer portions, forming lower spacer portions on the sides of said first gate structure, under said upper spacer portions, by selectively removing said first dielectric layer from said circuitry portion and leaving an array dielectric portion of said first dielectric layer on said control region;
• forming a protection mask by selectively etching said array dielectric portion after forming the upper spacer portions;
• forming a second conduction region of the bipolar transistor in the control region by implanting first conductivity-type dopants through a first opening in the protection mask after forming the upper spacer portions;
• and
• forming a control contact region of the bipolar transistor in the control region by implanting second conductivity-type doping agents through a second opening in the protection mask after forming the upper spacer portions.