Pixel structure of a display panel

A liquid crystal display panel, comprising:

• a first substrate comprising a plurality of pixel region, each pixel region comprising three sub-pixel regions, each pixel region comprising a pixel structure, the pixel structure comprising:
• three gate lines disposed along a first direction on the first substrate;
• a data line disposed along a second direction on the first substrate;
• three thin film transistors disposed on each of the sub-pixel regions respectively, each of the thin film transistors comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode of each of the thin film transistors is electrically connected to the corresponding gate line, and the source electrode of each of the thin film transistors is electrically connected to the data line;
• three pixel electrodes disposed in each of the sub-pixel regions respectively, and electrically connected to the corresponding drain electrode of each of the thin film transistors respectively;
• and
• a common line disposed on the first substrate, wherein the common line crosses the gate lines, partially overlaps with the gate lines, and the common line and the pixel electrodes partially overlap, forming three storage capacitors;
• a second substrate disposed opposite to the first substrate;
• and
• a liquid crystal layer interposed between the first substrate and the second substrate.

A pixel structure of a display panel formed on a substrate, the substrate comprising a plurality of sub-pixel regions, the pixel structure comprising:

• a gate line disposed along a first direction on the substrate;
• a data line disposed along a second direction on the substrate;
• a thin film transistor disposed in the sub-pixel region, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode, wherein the gate electrode of the thin film transistor is electrically connected to the gate line, and the source electrode of the thin film transistor is electrically connected to the data line;
• a pixel electrode disposed in the sub-pixel region and electrically connected to the drain electrode of the thin film transistor;
• and
• a common line disposed on the substrate and partially overlapping with the gate line, wherein the common line and the pixel electrode partially overlap, forming a storage capacitor.