System and Method for Frequency Translation With Harmonic Suppression Using Mixer Stages
AssigneeMicrotune, Inc.
InventorThomas L. Davis
Life of this patent
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Abstract
A method for generating phase signals includes triggering a phase register to output a binary number stored in the phase register, wherein the phase register is triggered based at least in part on a voltage signal provided by a voltage controlled oscillator. The method also includes providing an input signal to a decoder, wherein the input signal is based at least in part on the binary number output by the phase register and the decoder is operable to generate phase signals in response to the input signals. The method further includes incrementing the binary number stored in the phase register and repeating the triggering and providing steps after the binary number is incremented.
Claims22
A phase generation circuit, comprising:
- a decoder operable to:
- receive a plurality of input bits;
- and
- generate a plurality of phase signals in response to receiving the input bits;
- a phase register coupled to the decoder operable to:
- store a binary number;
- increment the binary number by a predetermined amount;
- and
- output the binary number to the decoder in response to a triggering signal, wherein the input bits of the decoder are based at least in part on the binary number output by the phase register;
- and
- a voltage controlled oscillator operable to generate a voltage signal at a frequency, wherein the triggering signal for the phase register is generated at least in part based on the frequency of the voltage controlled oscillator.
A method for generating phase signals, comprising:
- triggering a phase register to output a binary number stored in the phase register, wherein the phase register is triggered based at least in part on a voltage signal provided by a voltage controlled oscillator;
- providing an input signal to a decoder, wherein the input signal is based at least in part on the binary number output by the phase register and the decoder is operable to generate phase signals in response to the input signals;
- incrementing the binary number stored in the phase register;
- and
- repeating the triggering and providing steps after the binary number is incremented.
A circuit for frequency translating a radio frequency signal, comprising:
- a decoder operable to:
- receive a plurality of input bits;
- and
- generate a plurality of phase signals in response to receiving the input bits;
- a phase register coupled to the decoder operable to:
- store a binary number;
- increment the binary number by a predetermined amount;
- and
- output the binary number to the decoder in response to a triggering signal, wherein the input bits of the decoder are based at least in part on the binary number output by the phase register;
- a voltage controlled oscillator operable to generate a voltage signal at a frequency, wherein the triggering signal for the phase register is generated at least in part based on the frequency of the voltage oscillator;
- a prescaler coupled to the voltage controlled oscillator and the phase register operable to divide the frequency of the voltage signal by an integer and to provide the voltage signal as the triggering signal for the phase register;
- and
- a plurality of mixers coupled to the decoder, each mixer operable to receive one of the phase signals from the decoder and each mixer further operable to combine the respective phase signal weighted with a respective weighting factor for the mixer with a radio frequency signal.
The circuit of claim 21, further comprising an adder coupled to an input and an output of the phase register, the adder operable to:
- receive the binary number from the phase register;
- add the predetermined amount to the binary number to generate a new binary number;
- and
- provide the new binary number to the phase register, wherein the phase register increments by reading the new binary number from the adder.
Dependencies are inferred from the claim text.