Simultaneous bi-directional data transfer
AssigneeM2000
InventorsJean Barbier, Olivier V. Lepape
Life of this patent
Estimating the term…
Abstract
Embodiments provide methods, systems, and apparatuses including combinatorial or reconfigurable circuitry having input/output (I/O) circuitry with an I/O terminal and an input buffer. The I/O terminal receives a receive signal at a receive signal level that was transmitted from another integrated circuit at a transmitted signal level which is either a first or a second different signal level. The input buffer compares the receive signal to one or more reference signals to generate an input signal corresponding to the transmitted signal level based at least in part on the result of the comparison, even if the receive signal is received at a third signal level in between the first and the second signal level.
Claims21
An integrated circuit comprising:
- combinatorial or reconfigurable circuitry;
- and
- a set of input/output (I/O) circuitry coupled to the combinatorial or reconfigurable circuitry, wherein the I/O circuitry comprises an I/O terminal and an input buffer coupled to the I/O terminal, wherein the I/O terminal is configured to receive a receive signal at a receive signal level, the receive signal transmitted from another integrated circuit at a transmitted signal level which is either a first or a second different signal level, and wherein the input buffer comprises comparison circuitry configured to compare the receive signal to one or more reference signals to enable the input buffer to generate an input signal corresponding to the transmitted signal level based at least in part on the result of the comparison(s), even if the receive signal is received at a third signal level in between the first and the second signal level.
An apparatus comprising:
- means for receiving a receive signal at a receive signal level transmitted by another apparatus, the receive signal transmitted by the other apparatus at a transmit signal level that is either a high signal level or a low signal level different from the high signal level;
- means for comparing the receive signal to one or more reference signals to produce a comparison;
- and
- means for generating an input signal at an input signal level, corresponding to the transmit signal level, based at least upon the comparison even if the receive signal level is an intermediate signal level between the high and the low signal levels.
A system comprising:
- a signal wire;
- a first integrated circuit having a first set of I/O circuitry having a first I/O terminal coupled to the signal wire, a first input buffer, and a first output buffer to output a first output signal at a first output signal level via the first I/O terminal, wherein the first output signal level is either a high signal level or a low signal level;
- and
- a second integrated circuit comprising:
- a second set of input/output (I/O) circuitry comprising:
- a second I/O terminal coupled to the signal wire;
- a second output buffer to output a second output signal at a second output signal level on the signal wire via the second I/O terminal;
- and
- a second input buffer coupled to the second I/O terminal, and configured to receive the first output signal on the signal wire at a receive signal level, and wherein the second input buffer comprises comparison circuitry configured to compare the receive signal level to one or more reference signal levels to enable the second input buffer to generate an input signal corresponding to the first output signal based at least in part on the result of the comparison(s), even if the receive signal level is an intermediate signal level between the low and the high signal level.
Dependencies are inferred from the claim text.