M-bit race delay adder and method of operation
AssigneeSTMicroelectronics S.r.l.
InventorWilliam E. Ballachino
Life of this patent
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Abstract
There is disclosed an M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit. The M-bit adder comprises M adder cells arranged in R rows, wherein a least significant adder cell in a first one of the rows of adder cells receives a first data bit, Ax, from the first M-bit argument and a first data bit, Bx, from the second M-bit argument, and generates a first conditional carry-out bit, Cx(1), and a second conditional carry-out bit, Cx(0), wherein the Cx(1) bit is calculated assuming a row carry-out bit from a second row of adder cells preceding the first row is a 1 and the Cx(0) bit is calculated assuming the row carry-out bit from the second row is a 0.
Claims21
An M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit comprising:
- M adder cells arranged in R rows including a first row and R-1 subsequent rows, each row subsequent to the first row having more adder cells than a preceding row,
- wherein each row of adder cells includes a least significant adder cell and at least one subsequent adder cell,
- wherein each adder cell is configured to receive
- a data bit, Ax, from the first M-bit argument, and
- a data bit, Bx, from the second M-bit argument,
- wherein each adder cell subsequent to the least significant adder cell within each row subsequent to the first row is configured to receive
- a first conditional carry-in bit, Cx−1(1), from a preceding adder cell within the row, and
- a second conditional carry-in bit, Cx−1(0), from the preceding adder cell within the row, and
- wherein each adder cell within a row subsequent to the first row is configured to generates a first conditional carry-out bit, Cx(1), and a second conditional carry-out bit, Cx(0), wherein the Cx(1) bit is calculated assuming a carry-out bit from a most significant adder cell within the preceding row is a 1 and the Cx(0) bit is calculated assuming the carry-out bit from the most significant adder cell within the preceding row is a 0.
2-23. (canceled)
A data processor comprising:
- an instruction execution pipeline comprising N processing stages, each of said N processing stages capable of performing one of a plurality of execution steps associated with a pending instruction being executed by said instruction execution pipeline, wherein at least one of said N processing stages comprises an M-bit adder capable of n M-bit adder capable of receiving a first M-bit argument, a second M-bit argument, and a carry-in (CI) bit comprising:
- M adder cells arranged in R rows including a first row and R-1 subsequent rows, each row subsequent to the first row having more adder cells than a preceding row,
- wherein each row of adder cells includes a least significant adder cell and at least one subsequent adder cell,
- wherein each adder cell is configured to receive
- a data bit, Ax, from the first M-bit argument, and
- a data bit, Bx, from the second M-bit argument,
- wherein each adder cell subsequent to the least significant adder cell within each row subsequent to the first row is configured to receive
- a first conditional carry-in bit, Cx−1(1), from a preceding adder cell within the row, and
- a second conditional carry-in bit, Cx−1(0), from the preceding adder cell within the row, and
- wherein each adder cell within a row subsequent to the first row is configured to generates a first conditional carry-out bit, Cx(1), and a second conditional carry-out bit, Cx(0), wherein the Cx(1) bit is calculated assuming a carry-out bit from a most significant adder cell within the preceding row is a 1 and the Cx(0) bit is calculated assuming the carry-out bit from the most significant adder cell within the preceding row is a 0.
Dependencies are inferred from the claim text.