Microprocessor apparatus and method for persistent enablement of a secure execution mode

A microprocessor apparatus, for executing secure code within a secure execution environment, the microprocessor apparatus comprising:

• a secure non-volatile memory, configured to store a secure application program;
• and
• a microprocessor, coupled to said secure non-volatile memory via a private bus, configured to execute non-secure application programs and said secure application program, wherein said secure application program is executed exclusively within a secure execution mode, said microprocessor comprising:
• a bus interface unit, configured to accomplish system bus transactions over a system bus to access said non-secure applications in system memory;
• a secure non-volatile memory interface unit, configured to couple said microprocessor to said secure non-volatile memory via a private bus, wherein private bus transactions over said private bus to access said secure non-volatile memory are hidden from observation by system bus resources within said microprocessor and to any device coupled to said system bus;
• and
• a non-volatile enabled indicator register, configured indicate whether said microprocessor is within said secure execution mode or a non-secure execution mode, wherein contents of said non-volatile enabled indicator register persist through power removal and reapplication to said microprocessor.

A method for executing secure code within a secure execution environment, the method comprising:

• providing a secure non-volatile memory for storage of the secure code;
• storing the secure code within the secure non-volatile memory via private transactions accomplished over a private bus that is coupled to the secure non-volatile memory;
• initializing a secure execution mode within a microprocessor for execution of the secure code;
• recording that the secure execution mode is enabled in a non-volatile enabled indicator register;
• and
• fetching the secure code from the secure non-volatile memory over the private bus for execution by the microprocessor;
• wherein the private bus is isolated from all system bus resources within the microprocessor and external to the microprocessor, and wherein the private bus is observable and accessible exclusively by secure execution logic within the microprocessor.