Circuits and Methods for Clock and Data Recovery
AssigneeAvago Technologies Fiber IP (Singapore) Pte. Ltd.
InventorPeter Ho
Life of this patent
Estimating the term…
Abstract
A clock-data recovery circuit includes a phase rotator, a phase detector and a charge pump. The phase rotator receives first and second reference clocks and differential control signals. The phase rotator generates a modified clock signal responsive to the first and second reference clocks and the control signals. The phase detector receives a data signal and the modified clock signal. The phase detector generates a modified data signal and a phase error signal responsive to the data signal and the modified clock signal. The charge pump receives the phase error signal and generates the differential control signals, which direct the phase rotator to interpolate between select clock phases.
Claims20
A clock-data recovery circuit, comprising:
- a phase rotator configured to generate a modified clock signal responsive to a first reference clock signal, a second reference clock signal and first and second control signals;
- a phase detector configured to receive the modified clock signal and a data signal, the phase detector further configured to generate a modified data signal and a phase adjustment signal responsive to the modified clock signal and the data signal;
- and
- a charge pump configured to receive the phase adjustment signal and generate the first and second control signals.
A method for clock-data recovery, comprising:
- receiving a data signal;
- receiving a first reference clock signal;
- receiving a second reference clock signal 90° out of phase with the first reference clock signal;
- generating a modified clock signal responsive to the first and second reference clock signals;
- generating a modified data signal responsive to a timing relationship between the data signal and the modified clock signal;
- generating a phase error signal responsive to the timing relationship;
- using a multiple channel charge pump responsive to the phase error signal to generate a pair of control signals;
- and
- using the control signals to adjust the modified clock signal.
Dependencies are inferred from the claim text.