Semiconductor memory device
AssigneePanasonic Corporation
InventorsYukihiro KANEKO, Yoshihisa Kato
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Abstract
A memory cell includes a memory element including a MFSFET having a gate insulating film made of a ferroelectric film, and a selection switching element including a MISFET having a gate insulating film made of a paraelectric film. A load element for a read operation is connected in series to the memory cell. The ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween. The semiconductor film forms a common channel shared by the MFSFET and the MISFET. The load element includes a MISFET having a channel made of the semiconductor film or a resistance element having a resistor made of the semiconductor film.
Claims16
A semiconductor memory device comprising:
- a memory cell including a memory element including a first field effect transistor having a gate insulating film made of a ferroelectric film, and a selection switching element including a second field effect transistor having a gate insulating film made of a paraelectric film;
- and
- a load element for a read operation connected in series to the memory cell,
- wherein the ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween,
- the semiconductor film forms a common channel shared by the first field effect transistor and the second field effect transistor, and
- the load element includes a third field effect transistor having a channel made of the semiconductor film or a resistance element having a resistor made of the semiconductor film.
A semiconductor memory device comprising:
- a memory element including a first field effect transistor having a gate insulating film made of a ferroelectric film;
- and
- a load element for a read operation including a second field effect transistor having a gate insulating film made of a paraelectric film, and connected in series to the memory element,
- wherein the ferroelectric film and the paraelectric film are stacked with a semiconductor film being interposed therebetween, and
- the semiconductor film forms a common channel shared by the first field effect transistor and the second field effect transistor.
A semiconductor memory device comprising:
- a memory cell including a first field effect transistor having a gate insulating film made of a ferroelectric film and a channel made of a semiconductor film;
- and
- a load element for a read operation connected in series to the memory cell,
- wherein the memory cell stores, as multi-level data, at least three channel resistance values corresponding to respective polarization states of the ferroelectric film,
- the multi-level data stored in the memory cell is read by detecting an intermediate potential between the memory cell and the load element, and
- the read operation is performed by determining the multi-level data stored in the memory cell in order of the channel resistance value, highest first.
Dependencies are inferred from the claim text.