Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorSusumu TAMON
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Abstract
According to an aspect of the present invention, there is provided a semiconductor device including: first and second blocks that each includes a word line group of first to N-th word lines, the word lines extending in a given direction, the word lines having a first width, the first and second blocks being adjacent to and in parallel with each other in a crossing direction so that an inter-block area is interposed therebetween and so that the word line groups are symmetrical with respect to the inter-block area; and a first wirings that are formed in a first wiring layer positioned above the word lines to have a second width wider than the first width and that connect a k-th word line of the first block and a k-th word line of the second block.
Claims19
A semiconductor device comprising:
- first and second blocks that each includes a word line group of first to N-th word lines, N being integer equal to or larger than 2, the word lines extending in a given direction in parallel with one another in a crossing direction intersecting with the given direction, the word lines having a first width, the first and second blocks being adjacent to and in parallel with each other in the crossing direction so that an inter-block area is interposed therebetween and so that the word line groups are symmetrical with respect to the inter-block area;
- and
- a plurality of first wirings that are formed in a first wiring layer positioned above the word lines to have a second width wider than the first width and that connect a k-th word line of the first block and a k-th word line of the second block, k being integer equal to or larger than 1 and lower than or equal to N.
A semiconductor device comprising:
- a semiconductor substrate;
- a first block including:
- a plurality of first memory cell transistors arranged in matrix;
- and
- a plurality of first word lines connecting the first memory cell transistors in a first direction;
- a second block including:
- a plurality of second memory cell transistors that are adjacent to the first block in a second direction intersecting the first direction and that are arranged in matrix;
- and
- a plurality of second word lines connecting the second memory cell transistors in the first direction;
- and
- a plurality of first wirings that are formed in a first wiring layer positioned above the first wiring lines and the second word lines and that respectively connect a k-th one of the first word lines and a k-th one of the second word lines, k being integer equal to or larger than 1 and lower than or equal to N.
Dependencies are inferred from the claim text.