Digital phase detector and phase-locked loop

A digital phase detector comprising:

• a multiplier that, when a ratio of a frequency of a first clock to a frequency of a second clock is close to an integer K, receives the first clock and multiplies the first clock by M/N, where N is an integer relatively prime to the integer K and M is an integer relatively prime to the integer N;
• a pulse counter for receiving an output clock of the multiplier and the second clock, and counting the number of pulses per cycle of the second clock;
• a first adder for outputting a difference between an output of the pulse counter and a fixed value;
• and
• an accumulator for sequentially integrating an output of the first adder for each cycle of the second clock,
• wherein the pulse counter includes:
• a flip flop for latching the second clock by the output clock of the multiplier;
• a differential circuit for differentiating an output of the flip flop;
• a counter that is initialized by an output of the differential circuit to perform a counting operation;
• a first latch circuit for latching an output of the counter by the output of the differential circuit;
• (N−1) second latch circuits for sequentially latching an output of the first or second latch circuit by the output of the differential circuit;
• and
• a second adder for adding the outputs of the first and second latch circuits.

A digital phase detector comprising:

• a multiplier that, when a ratio of a frequency of a first clock to a frequency of a second clock is close to an integer K, receives the first clock and multiplies the first clock by M/N, where N is an integer relatively prime to the integer K and M is an integer relatively prime to the integer N;
• a pulse counter for receiving an output clock of the multiplier and the second clock, and counting the number of pulses per cycle of the second clock;
• a first adder for outputting a difference between an output of the pulse counter and a fixed value;
• and
• an accumulator for sequentially integrating an output of the first adder for each cycle of the second clock,
• wherein the output clock of the multiplier includes L (L is two or larger positive integers) sub clocks phase shifted with respect to each other by equal intervals,
• wherein the pulse counter includes:
• L flip flops for latching the second clock by the sub clocks;
• L differential circuits for differentiating outputs of the flip flops;
• L counters that are initialized by outputs of the differential circuits to perform a counting operation;
• L first latch circuits for latching the outputs of the counters by the outputs of the differential circuits;
• L·(N−1) second latch circuits for sequentially latching outputs of the first or second latch circuits by the outputs of the differential circuits;
• a second adder for adding the outputs of the L first latch circuits, and the outputs of the L·(N−1) second latch circuits.