Self-Biased Phase Locked Loop

A self-biased Phase Locked Loop, PLL, comprising:

• a Phase Frequency Detector, PFD, adapted to detect a frequency difference and a phrase difference between an input signal and a feedback signal and to generate a pulse control signal;
• a Charge Pump, CP, adapted to generate a charging or discharging current which equals to a first control current input to the CP according to the pulse control signal output from the PFD;
• a Loop Filter, LF, adapted to output a first control voltage so as to raise the first control voltage when the CP outputs the charging current and lower the first control voltage when the CP outputs the discharging current, the resistance of the LF is controlled by the first control voltage and a second control voltage which is adjusted according to the first control voltage and a second control current input to the LF;
• a Voltage Control Oscillator, VCO, adapted to generate an oscillation voltage and a bias current according to the first control voltage output from the LF so as to increase an oscillation frequency of an output signal when the oscillation voltage is increased and decrease the oscillation frequency of the output signal when the oscillation voltage is lowered;
• a divider adapted to perform a frequency division on the output signal of the VCO and generate the feedback signal input to the PFD;
• and
• a bias current converter adapted to convert the bias current generated by the VCO into the first control current input to the CP and the second control current input to the LF, wherein the first control current equals to the ratio of the bias current to a constant, and the second control current equals to the ratio of the bias current to a frequency division factor of the divider.