Integrated circuit arrangement for generating a digital variable gain control signal
AssigneeNational Semiconductor Germany AG
InventorsSTEPHAN MECHNIG, VITTORIO MELINI
Life of this patent
Estimating the term…
Abstract
The invention proposes an integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising: a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile, a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and a programming interface (20) for programming the memory (16). The integrated circuit arrangement (10) in accordance with the invention makes it possible to read out e.g. a gain characteristic as needed at the time for an ultrasound or radar application of a VGA in fast response at a defined rate from the memory (16).
Claims11
An integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising:
- a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile,
- a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and
- a digital programming interface (20) for programming the memory (16).
An integrated circuit arrangement (10) for generating a digital variable gain control signal (SA) for a digitally variable gain amplifier (14), comprising:
- a memory (16) for storing at least one digital signal sequence (DS) defining a time gain profile,
- a controller (18) for generating the digital variable gain control signal (SA) by reading out the memory (16), and
- a digital programming interface (20) for programming the memory (16),
- wherein the controller (18) is programmable and works by making use of control parameters stored in the memory (16),
- wherein the memory (16) comprises a first memory portion (16a-1) for storing the at least one digital signal sequence (DS) and at least one second memory portion (16a-2) for storing control parameters of the controller (18) and of the programming interface (20).
Dependencies are inferred from the claim text.