Transconductance amplifier
AssigneeAsahi Kasei EMD Corporation
InventorYusuke Aiba
Life of this patent
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Abstract
An embodiment of the present invention has a differential pair including a first and second MOS transistors having their sources grounded; a third and fourth transistor with their source terminals connected to drain terminals of the first and second transistors, respectively; a voltage generating circuit for outputting tuning and common voltage so that the ratio between the common and tuning voltage is constant; and a differential pair input voltage generating circuit that receives the input and common voltage to output voltages Vip and Vin to gate terminals of the first and second transistors, respectively. The gate terminal of the fourth transistor is connected to the gate terminal of the third transistor, and the tuning voltage is input to the two terminals.
Claims10
1-10. (canceled)
A transconductance amplifier for supplying output current in proportion to input voltage, said transconductance amplifier comprising:
- a differential pair including source grounded first and second MOS transistors operating in triode region;
- a third MOS transistor that operates in saturation region with a source terminal thereof connected to a drain terminal of said first MOS transistor;
- a fourth MOS transistor that operates in saturation region with a source terminal thereof connected to a drain terminal of said second MOS transistor and a gate terminal thereof connected to a gate terminal of said third MOS transistor;
- a voltage generating circuit for outputting tuning voltage to be input to gate terminals of said third and fourth MOS transistors, and common voltage for generating first voltage and second voltage to be input to said differential pair in such a manner that a ratio between the tuning voltage and the common voltage is constant;
- and
- a differential pair input voltage generating circuit that receives the common voltage, outputting the first voltage to the gate terminal of said first MOS transistor and the second voltage to the gate terminal of said second MOS transistor, wherein
- the second voltage equals 2×(the common voltage)−(the first voltage);
- the input voltage equals the difference between the first voltage and the second voltage;
- and
- the output current equals the difference between a first drain-to-source current of said first and third MOS transistors and a second drain-to-source current of said second and fourth MOS transistors.
Dependencies are inferred from the claim text.