Self-Identifying Stacked Die Semiconductor Components

An integrated circuit, comprising:

• a decode circuit configured to pass at least one of a plurality of external control signals external to the integrated circuit as at least one integrated circuit control signals for the integrated circuit, wherein the decode circuit is configured to determine which of the at least one external control signals to pass as the at least one integrated circuit control signal in accordance with a plurality of internal control signals;
• and
• a connection node associated with each of the internal control signals, wherein a logic state of each internal control signals is set depending on whether its associated connection node is connected or not connected to a source external to the integrated circuit.

A multiple integrated circuit structure, comprising:

• a vertical stack of a plurality of integrated circuits;
• and
• a plurality of connectivity patterns between successive integrated circuits in the vertical stack, wherein each connectivity pattern is configured to indicate different first control signals to each of the integrated circuits.

A multiple integrated circuit structure, comprising:

• a vertical stack of a plurality of integrated circuits;
• and
• a plurality of connectivity patterns, wherein one of the connectivity patterns provide either connections or non-connections to connection nodes in an associated one of the integrated circuits to indicate to that integrated circuit its position in the vertical stack.