Bi-directional buffer and method for bi-directional buffering that reduce glitches due to feedback

A method for bi-directional buffering, comprising:

• (a) controlling the turning on of one transistor at a time, of a first pair of transistors, to enable a second input/output (I/O) terminal to follow a first I/O terminal;
• (b) controlling the turning on of one transistor at a time, of a second pair of transistors, to enable the first I/O terminal to follow the second I/O terminal;
• (c) detecting whether a direction of a signal is from the first I/O terminal to the second I/O terminal, or vise versa from the second I/O terminal to the first I/O terminal;
• (d) in response to detecting that the direction of the signal is from the first I/O terminal to the second I/O terminal, at least temporarily preventing the turning on of the second pair of transistors by at least temporarily disabling at least one one-shot while the direction of the signal is from the first I/O terminal to the second I/O terminal to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal;
• and
• (e) in response to detecting that the direction of the signal is from the second I/O terminal to the first I/O terminal, at least temporarily preventing the turning on of the first pair of transistors by at least temporarily disabling at least one further one-shot while the direction of the signal is from the second I/O terminal to the first I/O terminal to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.

A method for bi-directional buffering, comprising:

• (a) using a first pair of one-shots to control the turning on of one transistor at a time, of a first pair of transistors, to enable a second input/output (I/O) terminal to follow a first I/O terminal;
• and
• (b) using a second pair of one-shots to control the turning on of one transistor at a time, of a second pair of transistors, to enable the first I/O terminal to follow the second I/O terminal;
• (c) detecting whether a direction of a signal is from the first I/O terminal to the second I/O terminal, or vise versa from the second I/O terminal to the first I/O terminal;
• (d) in response to detecting that the direction of the signal is from the first I/O terminal to the second I/O terminal, at least temporarily disabling the second pair of one-shots while the direction of the signal is from the first I/O terminal to the second I/O terminal to thereby at least temporarily prevent the turning on of the second pair of transistors while the direction of the signal is from the first I/O terminal to the second I/O terminal to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal;
• and
• (e) in response to detecting that the direction of the signal is from the second I/O terminal to the first I/O terminal, at least temporarily disabling the first pair of one-shots while the direction of the signal is from the second I/O terminal to the first I/O terminal to thereby at least temporarily prevent the turning on of the first pair of transistors while the direction of the signal is from the second I/O terminal to the first I/O terminal to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.

A bi-directional buffer, comprising:

• a first pull-up transistor connected between a first input/output (I/O) terminal and a first high voltage rail;
• a first pull-down transistor connected between the first I/O terminal and a first low voltage rail;
• a second pull-up transistor connected between a second input/output (I/O) terminal and a second high voltage rail;
• a second pull-down transistor connected between the second I/O terminal and a second low voltage rail;
• a first pair of one-shots;
• a second pair of one-shots;
• a first buffer having an input connected to the first I/O terminal and an output connected to inputs of the first pair of one-shots;
• a second buffer having an input connected to the second I/O terminal and an output connected to inputs of the second pair of one-shots;
• wherein an output of one of the one-shots, of the first pair of one-shots, is connected to a control terminal of the first pull-up transistor;
• wherein an output of the other one of the one-shots, of the first pair of one-shots, is connected to a control terminal of the first pull-down transistor;
• wherein an output of one of the one-shots, of the second pair of one-shots, is connected to a control terminal of the second pull-up transistor;
• wherein an output of the other one of the one-shots, of the second pair of one-shots, is connected to a control terminal of the second pull-down transistor.

A bi-directional buffer, comprising:

• a first pull-up transistor having a current path connected between a first input/output (I/O) terminal and a first high voltage rail;
• a first pull-down transistor having a current path connected between the first I/O terminal and a first low voltage rail;
• a second pull-up transistor having a current path connected between a second I/O terminal and a second high voltage rail;
• a second pull-down transistor having a current path connected between the second I/O terminal and a second low voltage rail;
• a first buffer having an input connected to the first I/O terminal and having an output;
• a first one-shot having an input that receives the output of the first buffer, and having an output the drives a control terminal of the second pull-up transistor;
• a second one-shot having an input that receives the output of the first buffer, and having an output that drives a control terminal of the second pull-down transistor;
• a second buffer having an input connected to the second I/O terminal and having an output;
• a third one-shot having an input that receives the output of the second buffer, and having an output the drives a control terminal of the first pull-up transistor;
• a fourth one-shot having an input that receives the output of the second buffer, and having an output that drives a control terminal of the first pull-down transistor;
• a direction detector that detects whether a direction of a signal is from the first I/O terminal to the second I/O terminal, or vise versa from the second I/O terminal to the first I/O terminal;
• wherein the direction detector, in response to detecting that the direction of the signal is from the first I/O terminal to the second I/O terminal, at least temporarily prevents the turning on of the first pull-up transistor and the first pull-down transistor while the direction of the signal is from the first I/O terminal to the second I/O terminal;
• and
• wherein the direction detector, in response to detecting that the direction of the signal is from the second I/O terminal to the first I/O terminal, at least temporarily prevents the turning on of the second pull-up transistor and the second pull-down transistor while the direction of the signal is from the second I/O terminal to the first I/O terminal.