Signal output circuit and selector circuit using the same
AssigneeElpida Memory, Inc.
InventorYasuhiro Takai
Life of this patent
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Abstract
A signal output circuit adapted to a selector circuit is constituted of an inverter circuit which activates propagation of an input signal therethrough in an active level of a control signal and which inactivates it in an inactive level of the control signal, and a control circuit which maintains the input terminal of the inverter circuit at a predetermined potential irrespective of the level of the input signal in the inactive level of the control signal. This achieves high-speed and high-precision propagation of the input signal. The selector circuit is formed using a plurality of signal output circuits so as to selectively output one of first and second input signals in response to the control signal.
Claims16
A signal output circuit comprising:
- an inverter circuit receiving a gate signal and a control signal, wherein the inverter circuit allows the gate signal to propagate therethrough in an active level of the control signal while the inverter circuit blocks the gate signal in an inactive level of the control signal;
- and
- a control circuit maintaining an input terminal of the inverter circuit at a predetermined potential irrespective of a level of an input signal in the inactive level of the control signal.
A selector circuit comprising:
- a first inverter circuit which receives a first input signal and a first control signal and which activates propagation of the first input signal therethrough in an active level of the first control signal while inactivating it in an inactive level of the first control signal;
- a second inverter circuit which receives a second input signal and a second control signal and which activates propagation of the second input signal therethrough in an active level of the second control signal while inactivating it in an inactive level of the second control signal;
- and
- a control circuit which maintains an input terminal of the first inverter circuit at a predetermined potential irrespective of a level of the first input signal in the inactive level of the first control signal and which maintains an input terminal of the second inverter circuit at the predetermined potential irrespective of a level of the second input signal in the inactive level of the second control signal.
A signal output circuit comprising:
- a gate circuit which activates propagation of an input signal therethrough in an active level of a control signal and which inactivates it in an inactive level of the control signal, wherein an output signal of the gate circuit is maintained at a prescribed potential irrespective of a level of the input signal in the inactive level of the control signal;
- a first transistor coupled with a first level, which is turned off in the inactive level of the control signal;
- a second transistor connected in series with the first transistor;
- and
- a third transistor coupled with a second level, whose gate is coupled with a gate of the second transistor so as to receive the output signal of the gate circuit and which is connected in series with the second transistor in connection with an output terminal.
Dependencies are inferred from the claim text.