Voltage level shift circuit and semiconductor integrated circuit

A voltage level shift circuit, comprising:

• a first source follower circuit including:
• a first P-channel enhancement type MOS transistor (M21), a gate terminal of which is connected to a first voltage signal input terminal (In11) and a drain terminal of which is grounded;
• and
• a second P-channel enhancement type MOS transistor (M22), a drain terminal of which is connected to a source terminal of the first P-channel enhancement type MOS transistor (M21) and to a first voltage signal output terminal (Out11) to be a constant current load;
• a second source follower circuit including:
• a third P-channel enhancement type MOS transistor (M23), a gate terminal of which is connected to a second voltage signal input terminal (In12) and a drain terminal of which is grounded;
• and
• a fourth P-channel enhancement type MOS transistor (M24), a drain terminal of which is connected to a source terminal of the third P-channel enhancement type MOS transistor (M23) and to a second voltage signal output terminal (Out12) to be a constant current load;
• a cascode circuit formed of an N-channel depletion type MOS transistor (M26), a gate terminal of which is connected to a fixed potential, a source terminal of which is connected to a source terminal of the second P-channel enhancement type MOS transistor (M22) and to a source terminal of the fourth P-channel enhancement type MOS transistor (M24), and a drain terminal of which is fixed to power supply voltage;
• and
• a fifth P-channel enhancement type MOS transistor (M25) which, together with the second P-channel enhancement type MOS transistor (M22) and the fourth P-channel enhancement type MOS transistor (M24), forms a current mirror circuit, for causing a current which is the same as a reference current (Iref) to flow through the second P-channel enhancement type MOS transistor (M22) and the fourth P-channel enhancement type MOS transistor (M24).