Semiconductor device
AssigneeElpida Memory, Inc.
InventorKazutaka MIYANO
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first duty determining circuit (20) and a second duty determining circuit (30). The first duty determining circuit (20) determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and updates the duty correction condition for the input signal on the basis of the first determination result. The second duty determining circuit (30) determines the duty correction condition for the input signal in a second predetermined cycle shorter than first predetermined cycle to obtain a second determination result and updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.
Claims20
A semiconductor device comprising:
- a first duty determining circuit that determines a duty correction condition for an input signal in a first predetermined cycle longer than a cycle of the input signal to obtain a first determination result and that updates the duty correction condition for the input signal on the basis of the first determination result;
- and
- a second duty determining circuit that determines the duty correction condition for the input signal in a second predetermined cycle shorter than the first predetermined cycle to obtain a second determination result and that updates the duty correction condition for the input signal only when the second determination result is fixed during a predetermined period.
A device comprising:
- a first duty detection circuit that detects a duty ratio of an input signal and outputs a first signal to adjust the duty ratio of the input signal, the duty ratio of the input signal being updated in response to the first signal in every first predetermined period;
- and
- a second duty detection circuit that detects the duty ratio of the input signal and outputs a second signal to adjust the duty ratio of the input signal, the duty ratio of the input signal being kept without being updated in response to the second signal when the second signal changes from a first logic level to a second logic level in a second predetermined period.
A device comprising:
- a control circuit that selects a first duty detection circuit to adjust a duty ratio of an input signal in a first period and selects a second duty detection circuit to adjust the duty ratio of the input signal in a second period following the first period.
Dependencies are inferred from the claim text.