Duty correction circuit

A duty correction circuit comprising:

• a plurality of delay circuits which are coupled together in a cascade-connection manner so as to convert an input clock signal into an output clock signal;
• a duty detection circuit detecting a duty ratio of the output clock signal;
• and
• a bias circuit supplying a first bias voltage or a second bias voltage to each of the delay circuits based on a detection result of the duty detection circuit,
• wherein each of the delay circuits includes
• a first inverter including a first transistor, a second transistor, and a third transistor of different conduction types, wherein the first transistor whose gate receives the input clock signal is connected between a first voltage and a first output terminal, the second transistor whose gate receives the input clock signal is connected to a second voltage, and the third transistor is connected in series to the first transistor in connection with the first output terminal,
• a second inverter including a fourth transistor, a fifth transistor, and a sixth transistor of different conduction types, wherein the fourth transistor whose gate is connected to the first output terminal is connected between the first voltage and a second output terminal outputting the output clock signal, the fifth transistor whose gate is connected to the first output terminal is connected to the second voltage, and the sixth transistor is connected in series to the fourth transistor in connection with the second output terminal,
• wherein the first bias voltage is supplied to a gate of the third transistor, while the second bias voltage is supplied to a gate of the sixth transistor, and
• wherein the input clock signal is sequentially delayed by each of the delay circuits and are converted into the output clock signal whose duty ratio is corrected based on the first bias signal or the second bias signal.